Rename "nxp,kinetis-lpuart" compatible to "nxp,lpuart" to remove the
device family from its name.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Logging with STMESP frontend is using custom logging header feature.
Put that specific header file in a custom path which is added to the
build only if that logging frontend is used.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Combine BLE and 802.15.4 monolithic build under a single config to make
it less error prone.
The choice between a BLE/802.15.4 combo firmware and a BLE only firmware
is done depending on the Soc (like RW610 vs RW612).
Signed-off-by: Axel Le Bourhis <axel.lebourhis@nxp.com>
Add 'turbo' logging feature. When enabled, short logs (no argument
or one numeric, 32 bit argument) are handled in a special way that
is much faster than the default one (5-10x faster). Additionally,
there is an option to remove all other logs from the system which
allows to not include almost any logging framework code in the
binary (~170 bytes of code is needed). It may be especially
valueable for memory constraint targets (ppr, flpr) where with
only 170 byte of code (+code for each log message) we can provide
limited formatted string logging support.
'Turbo' logging is using following to achieve that:
- logging strings are put into a memory section and additional
memory section is created which holds addresses of those strings.
Index in that array is used to identify a string (32 bit address
is encoded into a smaller number, 15 bits is more than enough).
This index is used for a STMESP register set (there are 2^16
available). So STMESP channel encodes string.
- Logging level is stringified and prepended to a string
- Source ID is encoded by using DM16 (so far not used).
- Log without arguments is written as DMTS16
- Log with one argumetn is written as DM16+DMTS32
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
This workaround will be replaced with a variant
executed at SystemInit() level, once MDK implements it.
Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
- Adds a flash runner configuration for mcxn/c/a/w
used for sysbuild multi-image projects.
- Solves sysbuild issue with multiple resets and mass erases.
Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
smp_log usage should be only used when SMP is enabled.
This is currently causing build issues after the fix
provided by #82377
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add CONFIG_MRAM_LATENCY_AUTO_REQ. When option is enabled then module
requests no latency during the initialization. This option might be
useful for cases where we want to achieve maximum performance and
want to avoid controlling MRAM in the code.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Replaces hard-coded memory addresses and sizes with macros that retrieve
such values from the device tree.
Signed-off-by: Marcio Ribeiro <marcio.ribeiro@espressif.com>
On NXP RT1170 SOC, ADC ETC exists but it can not be enabled because
of dependency on HAS_MCUX_ADC_ETC.
Also, ADC ETC should only work with ADC together, there is no use
case to run it standalone.
Fixes:#81466
Signed-off-by: Raymond Lei <raymond.lei@nxp.com>
In the IOMUXC controller, the PDRV field uses 0b0 to set the pin drive
to high, and 0b1 to set the pin to normal drive. Fix the pinctrl_soc.h
definitions for the iMXRT11xx parts to use the correct setting for this
register, based on the documentation for the pin control binding
Note that for PDRV type pins, this commit effectively switches their
drive strength setting.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Following the binding rename to "nxp,sysmpu", update the Kconfig
option to align with the binding name and to better reflect the
option's purpose.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
The MT8196 device has a newer interrupt controller that acts like the
legacy ones once initialized (see intc_mtk_adsp.c). But it has some
(only slightly) more complicated routing control that must be
initialized on reset, as the default is "don't deliver any interrupts
at all". Previous versions of the device integration worked becuase
they relied on a SOF binary to be loaded at boot, but obviously that
doesn't work for a Zephyr-based SOF firmware image.
Signed-off-by: Andy Ross <andyross@google.com>
This driver forgot to enable its interrupt, but has been working
becuase Zephyr apps were always run in a context where the interrupt
controller had been initialized by a SOF binary at boot.
Signed-off-by: Andy Ross <andyross@google.com>
This got missed. Set it correctly for hygiene, though very few things
use it. There is a spot in SOF where it's helpful to have a number for
"fasted cpu clock rate" and this is the best candidate.
Signed-off-by: Andy Ross <andyross@google.com>
I thought I was being clever letting the linker place the entry point
arbitrarily (since the hardware can set it to any value).
But it turns out that the upstream Linux SOF loader code is hard-wired
to start the DSP only at the first byte of SRAM, always, no matter
what entry point is listed in the rimage file. So until/unless this
is fixed, we need to add a trampoline at the start of SRAM (and
frustratingly that needs to be 1024 bytes long becuase of the
alignment requirements of the vector table that follows it, sigh...)
Signed-off-by: Andy Ross <andyross@google.com>
This is mostly a cut/paste copy of similar code in intel_adsp and imx,
which sadly can't be shared given the way the design works. Also
includes a bonus, slightly-passive-aggressive description of why that
is.
Signed-off-by: Andy Ross <andyross@google.com>
APPROTECT symbols were already aligned to nRF54L15,
but did not take into account similar SoCs like nRF54L05 or L10.
Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
Many NXP socs had the following defconfig:
```
config PINCTRL_IMX
default y if HAS_IMX_IOMUXC
depends on PINCTRL
```
However, the PINCTRL_IMX option already has:
```
config PINCTRL_IMX
bool "Pin controller driver for iMX MCUs"
depends on DT_HAS_NXP_IMX_IOMUXC_ENABLED
depends on HAS_MCUX_IOMUXC || HAS_IMX_IOMUXC
default y
help
Enable pin controller driver for NXP iMX series MCUs
```
So the soc level defconfigs are redundant.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
This definition is deleted in the follwoing commit;
8233b70
as a part of "cleanup", however this definition is
used by smp_log
Signed-off-by: Arif Balik <arifbalik@outlook.com>
Correctly selects the Kconfig symbols for viper CPU clusters
instead of having a reverse hwmv1 setup where the symbol has
a choice
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
check if multiples UART instances with same irq are enabled
at same time then enable shared_interrupt handler.
set the default value of SHARED_IRQ_MAX_NUM_CLIENTS config if
we have more than 2 usarts instances enabled.
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
- Move selection of CONFIG_PINCTRL from soc to individual
drivers
- in accordance with issue #78619
Signed-off-by: McAtee Maxwell <maxwell.mcatee@infineon.com>
Gap filling in hex files are now disabled per default, and therefore
there is no reason to explicitly disable gap filling.
It has never been possible to disable gap filling in binary files.
Disabling gap filling would just result in the binary file to be gap
filled with the tool's default value, objcopy=0x00.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
Fixes a wrong placement of a Kconfig which was put into the
wrong file and was bleeding through to every board
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
This reverts commit 3d3ffa2c05.
The original commit aimed to prevent NULL pointer accesses by moving the
MMU mapping starting point one page later. However, this change has
caused a regression on PTL. Our DSP has registers with addresses lower
than 0x1000, and the firmware uses addresses starting from 0xC40. For
instance, the HDAMLDMICL register is located at 0xCC0, which is now
inaccessible due to the change.
Reverting this commit restores access to these critical registers and
resolves the regression issue.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Release HSI CLK48 semaphore when going to sleep to allow C2 (M0)
core to start and stop clock as needed while C1 core is not running.
CLK48 is shared between RNG and USB. RNG is needed by M0 during BLE
advertisement. If semaphore is locked, C2 core can start it when it
needs to but not stop it.
Fixes zephyrproject-rtos#69955.
Signed-off-by: Jonny Gellhaar <jonny.gellhaar@prevas.se>
These devices have an architecturally fixed 13 MHz clock device. But
thankfully you can put a default into a DTS binding so we don't have
to repeat it for all of them.
Signed-off-by: Andy Ross <andyross@google.com>
Add Zephyr support for the Audio DSP on the MT8196 SOC. This is a
very similar device to previous designs. Most of this patch is just
DTS.
The biggest delta is the more complicated second level interrupt
controller, though it is still able to be represented using some
vaguely clever DTS config over the older intc_mtk_adsp driver.
Also the memory layout is slightly different, requiring a little
indirection to set the initial boot stack address and log output
buffer. And the timer "irq_ack" register bits moved.
Signed-off-by: Andy Ross <andyross@google.com>
New platform has different mappings. Auto-detect rather than parse
dts or similar, as this is is really just a simple format for testing.
Signed-off-by: Andy Ross <andyross@google.com>
The early boot function got renamed to a pseudo-standard "z_prep_c",
but this isn't an actual API and doesn't have a prototype in the
headers anywhere, so the compiler started whining about an undeclared
function.
Signed-off-by: Andy Ross <andyross@google.com>
These are very similar devices to mt8195, minimal changes needed
beyond boilerplate configuration.
In the process, this reworks the board/soc layout to be HWMv2
compliant, with "adsp" becoming a CPU cluster beneath the SOC. So the
name of the boards to west become e.g. "mt8195/mt8195/adsp" (which can
be shortened to "mt8195//adsp" if desired).
Note that the cpuclk driver is not yet ported, it works only with 8195
(the clocking/power architecture seems similar between the parts, but
the graph of wells and clocks is different and historically these have
been three separate drivers in SOF). The biggest changes are in the
image/loader scripts, which needed some rework for cross-device
portability.
Signed-off-by: Andy Ross <andyross@google.com>
This is a feature of the 8195 DSP only, which is used only vestigially
by SOF to store data that nothing reads. The Linux kernel on the
other side uses a shared driver for all 81xx devices, which does not
expose the feature. It seems to work, but it's not worth maintaining
a driver in tree for legacy hardware that will never use it.
Signed-off-by: Andy Ross <andyross@google.com>
Wire the default printk output to the console at boot, just to be sure
we have stdio output good enough to get tests to pass.
Signed-off-by: Andy Ross <andyross@google.com>
Introduce `CONFIG_RISCV_GP_PURPOSE` choice to make sure that only
one of `CONFIG_RISCV_GP` or `CONFIG_RISCV_CURRENT_VIA_GP` can be
enabled, instead of relying of dependencies.
To do that, introduce a new
`CONFIG_RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING` that can be selected
by SoC when it implemented global pointer (GP) initialization for
relative addressing in its linker.
`CONFIG_RISCV_GP` will be the default choice when
`CONFIG_RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING=y`
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
Silicon Labs Series 2 and newer devices do alternate function
configuration fundamentally differently from Series 0 and 1. Pin routing
is done in a centralized fashion in the GPIO peripheral, as opposed to
having ROUTE registers in every peripheral. The concept of alternate
function location numbers also does not exist, functions are directly
assigned to GPIOs by their port and pin number.
This commit adds a new pinctrl driver for devices that use DBUS. It fully
makes use of pinctrl design principles as outlined in the Zephyr
documentation. The previous driver hard-codes pin properties such as filter
and pull-up/down in the driver itself, while the new driver leaves this up
to the user as configurable DeviceTree properties. The previous driver has
hard-coded support for UART, SPI and I2C, while the new driver has generic
support for all DBUS signals.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
FH4X SoC type contains improvements in ROM code that
can save up to 35kB of memory.
Update hal_espressif in order to select proper linker
file based on upon SoC model.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
- Disables on reset NMI and EzPort.
- Fixes possible reset and power-on issues.
- Already applied for K64, now applying for the rest of Kinetis.
Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
- Trace32 runner: no need to configure TE bit in CFG_CORE
register in the cmm start-up script, it can be configured
at Zephyr start-up code when required (via SCTRL register)
- MPU static regions also needs to be updated for XIP and
non-XIP
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
Use Zephyr cache API to initialize cache as done for
various platforms. Enabling CACHE_MANAGEMENT by default
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
Due to the possibility of simultaneous accesess to LRCCONF registers,
additional management is required.
Signed-off-by: Adam Kondraciuk <adam.kondraciuk@nordicsemi.no>
This commit adds the pinctrl driver for WCH CH32V003.
Signed-off-by: Michael Hope <michaelh@juju.nz>
Signed-off-by: Dhiru Kholia <dhiru.kholia@gmail.com>
This puts the syscall helpers into the vector code section, and
is a tiny TLB optimization. Before this, worst case scenario is
that there would 2 instruction TLB misses when both the syscall
helpers and the vector code pages are not in TLB cache. With
this change, there would be at most 1 instruction TLB miss as
now the syscall helper and the vector code (which includes
exception handling code and xtensa_do_syscall()) are now in
the same page, and the same TLB entry.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Most likely there is no point of synchronizing RTC if net core is
not enabled. Same for the bootloader.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Put the default value for BT_AUTO_PHY_UPDATE and BT_AUTO_DATA_LEN_UPDATE
to "n" at SOC level since they cause "controller busy" due to starting
several parallel BLE procedures during connection by
"perform_auto_initiated_procedures" function. At the moment, ST controller
does not support parallelism, i.e. host should not initiate a new procedure
before previous one is completed.
Disable CONFIG_BT_HCI_ACL_FLOW_CONTROL at SOC level.
Signed-off-by: Ali Hozhabri <ali.hozhabri@st.com>
The `Kconfig.defconfig` is not good place for put `select PINCTRL`.
Drop `select PINCTL` from `Kconfig.defconfig` and add it at each
driver's Kconfig.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
The MMU mapping in SoC covers 0x0 which prevents catching NULL
pointer accesses. Since there are no hardware registers at
the very first page of memory, we move the starting point one
page later.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This change disables USB debug path at default, in order to prevent SoC
from entering debug mode when there is signal toggling on GPH5/GPH6.
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
`_current` is now functionally equals to `arch_curr_thread()`, remove
its usage in-tree and deprecate it instead of removing it outright,
as it has been with us since forever.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
NXP PORT IP instantiations often have different features absent, IE
input buffer, open drain, or slew rate support. Check if the relevant
PCR register bitmasks are defined in the common pin control file, and
define the bitmasks to 0x0 (no effect) if they are not. This allows us
to further consolidate the pinctrl_soc.h headers for SOCs using the PORT
IP.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
These two new ICs are variants of the nRF54L15 with different memory
sizes:
- nRF54L05: 500KB RRAM, 96KB RAM
- nRF54L10: 1022KB RRAM, 192KB RAM
- nRF54L15: 1524KB RRAM, 256KB RAM
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
There are many common options to all ICs of the 54L series. Consolidate
them in a single entry so that they do not need to be re-typed for each
SoC series member.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
add flexspi.c file to get flexspi clock rate.
Enable flexspi1 clock if don't boot from flash.
Use custom fixed mpu_regions.c file to config MPU for CM7
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
Split the cached area and assign both parts IROM and DROM meaning. This
is necessary to overcome the esptool section merging issues.
Signed-off-by: Marek Matej <marek.matej@espressif.com>
Add `hifive_unmatched//s7` (earlier selected by default, using
`hifive_unmatched`) and `hifive_unmatched//u74` targets.
Define work-area for other 4 cores in openocd.cfg
Update twister platform white/black lists, to support new targets
Signed-off-by: Jakub Wasilewski <jwasilewski@internships.antmicro.com>
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
Add `hifive_unleashed//e51` (earlier selected by default, using
`hifive_unleashed`) and `hifive_unleashed//u54` targets.
Define work-area for other 4 cores in openocd.cfg
Update twister platform white/black lists, to support new targets
Signed-off-by: Jakub Wasilewski <jwasilewski@internships.antmicro.com>
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
Remove the renesas,ra-pinctrl driver, which is no longer
needed after migrating to the FSP-based implementation.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Since the Option Setting Memory area is set in FSP, the Kconfig value
switches between using the FSP implementation or the existing
Option Setting Memory implementation.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Add a common part for AMD board ACP_6_0_ADSP.
Add support for ACP_6_0_ADSP BOARD,
which represents ACP_6_0 soc.
This has a 1 Xtensa HiFi5 core, with 200-800MHz
1.75 MB HP SRAM / 512 KB IRAM/DRAM,
1 x SP (I2S, PCM), 1 x BT (I2S, PCM), 1 x HS(I2S, PCM), DMIC as
audio interfaces.
Signed-off-by: DineshKumar Kalva <DineshKumar.Kalva@amd.com>
DCDC regulator on nRF54L may not always works as intended.
Tune the fix addressing that.
Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
DCDC regulator on nRF54L may not always works as intended.
Apply a fix addressing that.
Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
To configure APPROTECT on nRF54L15 different set of MDK symbols
must be used. Additionally, nRF54L15 does not support loading
APPROTECT configuration from the UICR in runtime.
Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
The nrfx_gppi module is an abstraction over nrfx_ppi and nrfx_dppi
drivers. It now has a Kconfig option that is separate from nrfx_dppi and
by default it enables all PPI/DPPI instances, if available.
Signed-off-by: Rafał Kuźnia <rafal.kuznia@nordicsemi.no>
The hal_nordic revision was updated to bring in NRFX v3.8.0.
Aligned the uses of single-instance API to use multi-instance instead.
Signed-off-by: Rafał Kuźnia <rafal.kuznia@nordicsemi.no>
This commit enables the TPIU clock source in Apollo3 and
Apollo4 soc initialization if LOG_BACKEND_SWO is used.
Signed-off-by: Aaron Ye <aye@ambiq.com>
What is changed?
Use CMSIS SystemCoreClock via a dedicated flag instead of using
soc flags.
Why do we need this change?
This change is part of cleaning soc specific code out of arch folder.
Signed-off-by: Sudan Landge <sudan.landge@arm.com>
The production version of the nRF54H20 SoC is now available, so remove
the initial Engineering B (EngB) preview version.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Nordic SoCs implement an event system, for which the system can
optimize for low latency/high power or low power.
Add soc level implementation of reference counted API which will
optimize for low latency if any part of the system requires it.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Before that fix the names for UDMA could be misleading.
With that fix the namespace is clear and easy to follow.
Same applies for peripheral addresses and pad config.
Signed-off-by: Sven Ginka <s.ginka@sensry.de>
Refactor out the `soc_early_init_hook()` function from `pma.c` to
`soc.c` which is always compiled so that it can be extended to run
other init functions easily in the future. Then, restore the function
in `pma.c` to `pma_init()`.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
The function `pma_init_per_core()`, as its name suggest, should be
run from every core, so call it from `soc_per_core_init_hook()`
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
The `soc_per_core_init_hook()` function now has `void` type after
da118b9, so it should just return without any value.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
Replace hardcoded register addresses and values in
asm_memory_management.h with Devicetree (DT) macros for LPSRAM
power-down operations. This change ensures that register addresses and
bank counts are dynamically obtained from the Devicetree, improving code
portability and reducing the risk of errors due to manual updates.
- Removed hardcoded LSPGCTL address definitions.
- Updated m_ace_lpsram_power_down_entire macro to use DT_NODELABEL to
fetch LPSRAM bank count and control register address
- Adjusted bit field extraction logic to align with the updated register
information from the Devicetree.
This commit aligns with the ongoing effort to utilize Devicetree for
hardware abstraction and to facilitate easier maintenance and updates to
the codebase.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Remove the m_ace_hpsram_power_change macro from asm_memory_management.h
as it is no longer used after refactoring the power_down function to
utilize the new m_ace_hpsram_power_down_entire macro. This cleanup helps
to reduce code complexity and maintainability.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Refactor the power_down function to utilize the newly introduced
m_ace_hpsram_power_down_entire macro for shutting down the entire
HPSRAM. This change simplifies the power-down process by replacing the
previous segment-based power gating mask approach with a single boolean
flag that indicates whether the entire HPSRAM should be disabled.
The function signature of power_down has been updated to accept the new
boolean flag, and the corresponding call sites have been modified to
pass the flag based on the CONFIG_ADSP_POWER_DOWN_HPSRAM Kconfig option.
Additionally, the assembly code has been cleaned up to remove the
now-obsolete hpsram_mask array and related logic.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Introduce a new assembly macro, m_ace_hpsram_power_down_entire, which
utilizes Zephyr Devicetree macros to power down the entire HPSRAM on
Intel ADSP ACE platforms.
This macro dynamically retrieves the HPSRAM bank count and control
register address from the Devicetree, streamlining the power-down
process. The macro is designed to iterate over all HPSRAM banks and
issue a power down command to each, ensuring a complete shutdown of the
HPSRAM when required by the system's power management policy.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This commit introduces the L2 Memory Capabilities (hsbcap) register node
to the Devicetree specifications for Intel ADSP ACE platforms. The
hsbcap register provides information on the general capabilities
associated with the L2 memory, which is critical for system
configuration and resource management. The hsbcap node has been added to
the Devicetree source files for ACE 1.5 (MTPM), ACE 2.0 (LNL), and ACE
3.0 (PTL) platforms.
In addition, the DFL2MM_REG macro in adsp_memory.h has been updated to
use the Devicetree node label for hsbcap, ensuring a consistent and
maintainable approach to accessing this register across the codebase.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This commit improves the readability of the power_down.S assembly file
by standardizing the indentation of the preprocessor definitions.
No functional changes have been made; this is purely a cosmetic update
to the code formatting.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This commit addresses an issue on platforms with an MMU where a
LoadStoreTLBMissCause exception occurs when accessing hardware registers
during the power-down process. The exception arises when attempting to
access the IPC register after HPSRAM has been powered down, leading to a
double exception: LoadStoreTLBMissCause followed by
InstrPIFDataErrorCause.
To resolve this, we preload the IPC register before shutting down
LPSRAM. This change prevents the double exception by ensuring that the
page table entries are correctly managed in the TLB before HPSRAM is
powered down and allowing the power-down sequence to complete
successfully.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
-Update formatting and contents of index.rst for cy8ckit_062s4
-Update formatting and contents of index.rst for cy8ckit_064s0s2_4343w
-Update formatting and contents of index.rst for cy8cproto_062_4343w
-Update formatting and contents of index.rst for cy8cproto_063_ble
-Update formatting and contents of index.rst for xmc45_relax_kit
-Update formatting and contents of index.rst for xmc47_relax_kit
-Change all instances of "PSoC" to "PSOC" for infineon platforms
Signed-off-by: McAtee Maxwell <maxwell.mcatee@infineon.com>
The linker script for this SoC was not including the LLEXT section
definitions when CONFIG_LLEXT was enabled. This patch adds the
necessary include directive to the linker script and fixes the build
issue identified by CI.
Signed-off-by: Luca Burelli <l.burelli@arduino.cc>
The linker script for this SoC was not including the LLEXT section
definitions when CONFIG_LLEXT was enabled. This patch adds the
missing include directive to the linker script.
Signed-off-by: Luca Burelli <l.burelli@arduino.cc>
Fix missing input/output enable flags on pinctrl macro, which
wouldn't allow for driver to see and apply flags configuration
made in the device tree.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
Updates and fixes to support APPCPU.
- fix ld scripts
- fix and update memory layout
- fix build issues
- fix sysbuild
Signed-off-by: Marek Matej <marek.matej@espressif.com>
The FRDM_MCXW71 Platform has a reserved IRQ as its
last IRQ, this test was using this IRQ to
test an interrupt and would not fire. This change
ensures the test does not use the reserved IRQ.
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
When option ARM_MPU is disabled exclude soc\nxp\imxrt\mpu_regions.c.
It is needed to remove constraints of SRAM and FLASH size.
Fixes#70920
Signed-off-by: Grixa Yrev <GrixaYrev@yandex.ru>
Busy-waiting for the result of the nrfs service calls can stall, so
let's use a callback that flags a semaphore instead. Since the API is
supposed to be callable in the context of pre-kernel, fallback to
busy-wait on that scenario.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
As for the IMX SOCs all the lines removed in this commit were
actually commented out so there's basically no change in code
behavior expected here.
The only affected SOCs family is therefore the Kinetis one.
Signed-off-by: Valerio Setti <vsetti@baylibre.com>
Make sure this expansion doesn't include `CONFIG_DCACHE_LINE_SIZE`,
which would be undefined and produce a build error.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
RT11xx SOC init should check to see if the zephyr flash node is
set to a device on the FLEXSPI bus to determine if the part is running
in XIP mode. This check was incorrect, so the FLEXSPI was being
reclocked in XIP mode to 24 MHz. Fix this check so the FlexSPI is not
downclocked.
Fixes#75702
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Usage of K_SPINLOCK with CONFIG_DEBUG=y seems to trigger a compiler
warning about request not always being initialized. Fallback to
k_spin_lock/unlock calls to fix this issue.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
This Kconfig has wrongly been added to defconfig files. It is not the
right place for it. It has never been the right place for it. Drivers
that need it should select the symbol in their Kconfig entries. Drop
PINCTL from Kconfig.defconfig and add proper select at Kconfig.sam*.
Fixes#78619
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
This Kconfig has wrongly been added to defconfig files. It is not the
right place for it. It has never been the right place for it. Drivers
that need it should select the symbol in their Kconfig entries. Drop
PINCTL from Kconfig.defconfig and add proper select at Kconfig.gd32.
Fixes#78619
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
It is enabled by default if we enable device PM, but we do not want
this, otherwise we get linker errors (PM subsys, fun guaranteed!).
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
This patch introduces a new flag to indicate if a peripheral belongs
to FAST_ACTIVE1 domain. This way, pinctrl knows when to request the
SLOW_ACTIVE domain (where CTRLSEL multiplexer resides).
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Do not select HAS_SEGGER_RTT unless the segger module is present. This
avoids a Kconfig error when SEGGER's debug module is not present in the
west manifest
Fixes#80529
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
There is a typo in the part number list for LPC55S69. The
LPC55S69JET98 should be LPC55S69JEV98.
Fixes#80541
Signed-off-by: David Leach <david.leach@nxp.com>
Larger image partitions require more space in DRAM due to
the increase in .bss.sector_buffers.
Each sector in .bss.sector_buffers consumes 16 bytes.
In the worst case scenario, such as with the ESP32S3 N32R8V,
which has 32 MB of flash and most likely 12 MB image partition,
an addition of 0xc000 should be sufficient to accommodate this.
Signed-off-by: Nik Schewtschuk <nikita.schewtschuk@smartmechatronics.de>
- Update GDMA and ADC drivers and remove deprecated entries.
- Rebased hal_espressif to latest bump sync.
- Added ESP Timer and Radio common config values
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Make sure all kconfig related to Wi-Fi is
in its driver area.
This commit also removes esp_timer_init() call
from Wi-Fi driver.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Files renaming done to better isolate zephyr related
functions from stm32 hal related functions
Signed-off-by: Alessandro Manganaro <alessandro.manganaro@st.com>
Make the SMPS_MODE define visible from drivers by moving it to soc.h
This define is for example used by the ADC driver to determine if sampling
should be synchronized with the SMPS clock.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
What is changed?
- Added a new mps3 board an555 for the soc corstone310.
The qualifier to build/run application with board mps3/an555 is
`mps3/corstone310/an555` for secure and
`mps3/corstone310/an555/ns` for non-secure.
- Added FVP variant to enable FVP testing with corstone310
and it uses the ARM FVP `FVP_Corstone_SSE-310`.
The qualifier to build/run application with FVP is
`mps3/corstone310/an555fvp` for secure and
`mps3/corstone310/an555fvp/ns` for non-secure.
Why do we need this change?
- This enables FVP support and testing for corstone310.
- A separate FVP variant was added for AN555 because, the TFM board
used for non-secure variant differs for FPGA and FVP.
TFM board `arm/mps3/corstone310/an555` should be used when testing
AN555 with FVP and `arm/mps3/corstone310/fvp` should be used when
testing with AN555 FPGA.
Signed-off-by: Sudan Landge <sudan.landge@arm.com>
What is changed?
- Added a new mps3 board an552 for the soc corstone300.
The qualifier to build/run application with board mps3/an552 is
`mps3/corstone300/an552` for secure and
`mps3/corstone300/an552/ns` for non-secure.
- Added FVP variant to enable FVP testing with corstone300
and it uses the ARM FVP `FVP_Corstone_SSE-300_Ethos-U55`.
The qualifier to build/run application with FVP is
`mps3/corstone300/fvp` for secure and
`mps3/corstone300/fvp/ns` for non-secure.
- Note: the qualifier to build/run application with board mps3/an547
is now changed to
`mps3/corstone300/an547` for secure and
`mps3/corstone300/an547/ns` for non-secure.
How is it changed?
- Moved common code from mps3/an547 to corstone300.
- Renamed soc for an547 to corstone300 and added
a new soc corstone300/an552.
Why do we need this change?
- This enables FVP support and testing for corstone300.
- SOC/qualifier for mps3/an547 was renamed to reduce code redundancy
- A separate FVP variant was added for AN552 because, the TFM board
used for non-secure variant differs for FPGA and FVP.
TFM board `arm/mps3/corstone300/fvp` should be used when testing
AN552 with FVP and `arm/mps3/corstone300/an552` should be used when
testing with AN552 FPGA.
Signed-off-by: Sudan Landge <sudan.landge@arm.com>
The current selected start-up time takes 8 seconds to initialize.
When xosc32 is used as main clock reference it blocks the whole
initializarion of the system by that amount of time. This patch
relax that condition setting the initialization time to 62ms.
Fixes#79949
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Only initialize the HFXO Manager HAL driver if the HFXO is enabled in
DeviceTree, the device uses SYSRTC for timekeeping, and Power Manager
is enabled. HFXO Manager integrates with the Sleeptimer HAL driver for
SYSRTC to autonomously wake the HFXO prior to Sleeptimer wakeup from
deep sleep. It is not needed on devices that don't have HFXO-SYSRTC
integration, and it is not needed if the application doesn't use deep
sleep.
Add missing call to init_hardware() prior to init().
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Rework Nordic specific S2RAM marking procedures.
The S2RAM marking procedures must not disrupt the stack due to
the TLS pointer not yet being initialized during their execution.
Signed-off-by: Adam Kondraciuk <adam.kondraciuk@nordicsemi.no>
Instead of fixing csi2rx clock frequencies, set them according to the
pixel rate got from the camera sensor.
Signed-off-by: Trung Hieu Le <trunghieu.le@nxp.com>
Signed-off-by: Phi Bang Nguyen <phibang.nguyen@nxp.com>
HAS_SEGGER_RTT Kconfix symbol is missing in NXP MCXC series Kconfig.
Add the symbol to fix and enable Segger RTT samples.
Signed-off-by: Michal Smola <michal.smola@nxp.com>
Power Manager no longer requires the Counter driver. This seems to have
been a hack to get the Sleeptimer HAL included in the build, as the
Sleeptimer is the real dependency of the Silabs Power Manager HAL.
Since Sleeptimer is now used for the OS timer, this hack is not needed.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Add OS timer implementation making use of the Sleeptimer HAL.
Sleeptimer integrates tightly with the Silabs Power Manager HAL,
and must be used as the OS timer to achieve optimal power consumption
when using the radio.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Add a pinctrl driver for Microchip MEC5 HAL based chips.
The driver removes the YAML enum "no change" property
value from the driver strength and slew rate properties.
Update the shared header file in mec soc common folder to
use a different Z_PINCTRL_STATE_PINCFG_INIT for MEC5.
Modifications to legacy MEC172x XEC PINCTRL will be in
a future PR.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
CMSIS SystemInit is not used in Zephyr. Implement the functionality
that isn't already done by Zephyr startup using soc_prep_hook().
The reason the lack of TrustZone init did not create immediately obvious
issues previously is that SMU faults can only happen if the SMU clock is
enabled.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Bandgap voltage is used for on die temperature measurement. Bandgap
buffer has to be enabled explicitly to get correct tempearature.
Enable the buffer if TEMP_KINETIS is selected.
Signed-off-by: Michal Smola <michal.smola@nxp.com>
The previous changes in
https://github.com/zephyrproject-rtos/zephyr/pull/74304
assumed that because this is also handled in
`bt_hci_transport_setup` that it shouldn't be done on
initialisation too.
However, if someone wants to develop their own app which
uses BT and also wants to enable the CPUNET by default this
KConfig should be available to them.
Signed-off-by: Sean Madigan <sean.madigan@nordicsemi.no>
Andes AE350 integrates 2 PLICs in the platfrom, one for external interrupt
and another for IPI. Adusted Kconfig for total IRQ numbers and support 2
aggregators in the 2nd level interrupt controller.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
The rom_mpu_padding section is incorrect NAPOT padding for the address of
__rodata_region_end when ROM_BASE is not 0x0, because __rom_region_start
is set to the offset of rom_start section.
Fixed this by use "__rom_region_start = ABSOLUTE(.);" to keep both
__rodata_region_end and __rom_region_start are absolute address.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
Add PCI device IDs for common Intel Raptor Lake variants and Alder Lake N.
These all have cAVS2.5 audio DSP.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Numerically sort the PCI DIDs for cAVS2.5 hardware. This follows
the convention in e.g. Linux and coreboot and eases maintainance. No
functional change.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
The "Detected cAVS 1.8+ hardware" message is misleading as it implies
some version of Intel cAVS hardware has been found, while in fact this
script supports also other types of hardware, including Intel ACE.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Clean up code documentation to drop references to platforms no longer
supported in the code. Continues the cleanup started in commit
086e4f84ed ("intel_adsp: cavstool: Remove
legacy code").
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
The default configuration for PINCTRL should not be set with
the other default configurations in .defconfig, instead select
a default value as part of defining the UART driver.
Signed-off-by: Andrew Davis <afd@ti.com>
Add initial SoC support for the TI J721E SoC series Cortex-R5 core.
TRM for J721e https://www.ti.com/lit/zip/spruil1
File: spruil1c.pdf
Signed-off-by: Prashanth S <slpp95prashanth@yahoo.com>
Signed-off-by: Andrew Davis <afd@ti.com>
The commit introduced regression for hsdk4xd platform.
The hsdk4xd SoC setup from soc_early_asm_init_percpu need to be done
in early code before any C code execution.
The current approach has multiple issues
- we call function (which can be easily implemented in C for
this or other SoC) from the place where we haven't setup stack
pointer (so we can't use stack) - which is very error-prone
- we never return back from soc_reset_hook on hsdk4xd platform
So let's just revert it for now. If any other ARC SoC need to use
soc_reset_hook - than it can be implemented properly.
This reverts commit 8c32a82e47.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
Series 2 always uses the device init HAL, while Series 0/1 never do.
Create a separate soc.c for Series 2 to make both versions easier to read.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Swap from the deprecated device_init_* functions to clock manager
for clock tree configuration. Populate config headers using
device tree representation of clock tree and oscillator config.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Switch EFR32MG21 to use the device init HAL. This makes the init sequence
the same as the rest of Series 2.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
On Series 2, set the SYS_CLOCK_HW_CYCLES_PER_SEC Kconfig option from
DeviceTree, rather than separately configuring it in board-level
defconfig.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Defconfig was only available at the vendor and series level,
make it possible to have family specific definitions too.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
The DC-DC converter was unconditionally initialized with default
settings on Series 2. Add device tree binding and nodes, and guard
call to init function. Map DT options to config header from HAL.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
- add ITCM definitions (for LinkServer) in board.cmake
- update of soc.c to support RAM images (stack pointer)
- doc update
Change applies to both versions of the MIMXRT1170 EVK
Signed-off-by: Yves Vandervennet <yves.vandervennet@nxp.com>
Extracts the max32 flashprog linker section to a dedicated linker script
that is conditionally included only when the flash driver is enabled.
This prepares max32 soc family to set SOC_LINKER_SCRIPT directly to the
common arm cortex-m linker script.
Signed-off-by: Maureen Helm <maureen.helm@analog.com>
This commit enables PMP on 64-bit SoCs from the SiFive Freedom SoC series
by default.
This change is needed to e.g. run the Userspace Hello World demo.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
Added a new driver to support SPI communication via EUSART. Since the
Silabs EFR32MG24 family SoCs have only one USART, EUSART support is
necessary for implementing SPI functionality.
Signed-off-by: Teresa Zepeda Ventura <teresa.zvent@gmail.com>
support the configurations which apply for LVDS pads
+ termination resistor
+ current reference control
+ rx current boost
Signed-off-by: Tu Nguyen Van <tu.nguyenvan@nxp.com>
IMXRT1062 bootrom reads boothdr initial vector table
from 0x60001000. In the CMAKE scatter linker scripts we put multiple
sections at offset 0x1000 in the rom. In linkers other than LD, we are
not guaranteed a particular order when placing these.
If we specify FIRST we can count on the .ivt coming first. The other
positions aren't as crucial.
From IMXRT1060RM.pdf 9.7.1
> The location of the IVT is the only fixed requirement by the ROM.
> The remainder or the image memory map is flexible and
> is determined by the contents of the IVT.
Signed-off-by: Robin Kastberg <robin.kastberg@iar.com>
The production version of the nRF54L15 SoC is now available, so remove
the initial Engineering A (EngA) preview version.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
This config will be used to indicate if a platform
has the support for monolithic BT feature.
Signed-off-by: Yassine El Aissaoui <yassine.elaissaoui@nxp.com>
New PDM, some present on nRF54L15 FP1, instances have
been added. Modified condfiguration file for nRF5340,
which now requires PDM0 instance.
Signed-off-by: Michał Stasiak <michal.stasiak@nordicsemi.no>
- Disables on reset NMI and EzPort.
- Fixes frdm-k64 SW3 user button on reset issue.
So it can be assigned to the mcuboot-button0 alias.
Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
ETR handler (for Coresight STM logging) is using console UART and
can act as the shell backend. When that happens default serial shell
backend shall be disabled (and it is by default enabled if there is
a zephyr,console chosen set.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
This commit applies several changes in the way "heap_runtime"
feature is used. It can't be split due to bisectability issues.
Whenever the feature is enabled, a new heap is created and
custom malloc/calloc/free functions are added into the build
system. Those functions are currently used for internal Wi-Fi and BLE
drivers only.
Such changes are described below:
1) Rename heap.c to esp_heap_runtime.c for better readability.
2) Rename RUNTIME_HEAP to HEAP_RUNTIME to make it similar to what is
available in Zephyr.
3) Add runtime heap to BT as such as Wi-Fi.
Fixes#79490Fixes#79470
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
This is a follow-up to commit 7a2ce2882a.
Do not enable clock control by default on nRF54H Series SoCs when
the system timer is present, because clock control is not needed
for this purpose there.
Add missing `default y` in the CLOCK_CONTROL_NRF2 Kconfig option that
enables compilation of clock control drivers for nRF54H Series.
This way modules that actually require clock control (like drivers
that use radio) will be able to enable it using the generic option
(CLOCK_CONTROL), not the above one that is specific for nRF54H.
Update accordingly applications that referenced the CLOCK_CONTROL_NRF2
option.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Fix definition for ROM status register for ACE1.5. The value should be
same as ACE2.0 and only different for ACE3.0.
Fixes: 6ad9b6ccab ("soc: intel_adsp: tools: add intel_adsp_ace30
support to cavstool.py")
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
SOC_FLASH_MCUX has additional dependencies for LPC55xxx CPUs, due to the
fact that the flash should be disabled when executing in nonsecure mode.
Since the merge of HWMv2, this dependency has been set incorrectly at
the SOC level, resulting in the IAP flash driver being enabled when
targeting CPU1, which is incorrect. Fix the Kconfig dependency to
resolve this issue.
Fixes#79576
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Enables the XSPIM2 rail when using GPIO bank N
Enables the XSPIM1 rail when using GPIO bank O or P
Enables the USBvoltage detector when using the GPIO M
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Service for powering peripherals that use GPIO pins
in the global power domains:
- Active Fast
- Active Slow
- Main Slow
Signed-off-by: Rafal Dyla <rafal.dyla@nordicsemi.no>
Commit b73c5578e3 ("soc: ti: move init code from SYS_INIT to hooks")
changed SYS_INIT to init hooks. For AM6x M4 target soc_prep_hook()
was added by mistake instead of soc_early_init_hook(), the platform needs
RAT translation initialized before any other operation and the platform
failed to boot with this change, fix this by replacing with
soc_early_init_hook()
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Some imx8 socs have cpu cluster entries for cores that
are not currently supported. Remove them.
Fixes#79027.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
nRF54H20 EngB is a re-label to the existing hardware revision for the
nRF54H20. nRF54H20 (whithout EngX) is becoming the final revision of the
SoC.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
The new GRTC reading manner of the SYSCOUNTER uses hardware mechanism which
allows to keep it alive when any of CPUs is not sleeping. Otherwise
the SYSCOUNTER goes into sleep mode. Thus there is no
longer need to maintain the `CONFIG_NRF_GRTC_SLEEP_ALLOWED` symbol, however
if the user wants to have the SYSCOUNTER enabled all the time the
`CONFIG_NRF_GRTC_ALWAYS_ON` can be used instead.
The nrfx_grtc driver no longer provides the `wakeup-read-sleep` reading
manner.
Also setting the GRTC clock source is performed by the nrfx_grtc driver so
it has been removed from the `sys_clock_driver_init()` function.
Signed-off-by: Adam Kondraciuk <adam.kondraciuk@nordicsemi.no>
Sets CONFIG_HAS_SEGGER_RTT on the max32 soc family to allow using RTT
backends in the logging, shell, and tracing subsystems.
Signed-off-by: Maureen Helm <maureen.helm@analog.com>
Asserts are by default enabled for tests but flpr and ppr are
small cores (<64k) and many tests does not fit in memory with
asserts enabled.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Add debug_slot_offset_by_type() for getting debug window slot offset
by type identifier. How to find the correct slot and what types there
are is documented here:
soc/intel/intel_adsp/common/include/adsp_debug_window.h
In a normal situation a client program would try to find a specific
slot right after DSP boot. Because of that the we can not expect it to
be there immediately. Instead we need to try multiple times and give
firmware some time to update the debug slot descriptor table.
Signed-off-by: Jyri Sarha <jyri.sarha@linux.intel.com>
The fw_is_alive() depends on 'dsp' global variable which is assigned
from map_regs() return value. To make fw_is_alive() and
wait_fw_entered(), that calls fw_is_alive(), callable from another
module, the 'dsp' variable needs to be passed as an argument.
Signed-off-by: Jyri Sarha <jyri.sarha@linux.intel.com>
map_reg() depends on args global variable for knowing it should
load a new firmware or just stand by for logging or Zephyr
shell. The map_regs() code is the very first step to access the
DSP memory, it nees to be shareable if the code is to be accessed
from another python module.
Signed-off-by: Jyri Sarha <jyri.sarha@linux.intel.com>
Do not force argsparse code to all modules importing cavstool.py. The
commit moves argparse code into a separate function, and calls it from
'if __name__ == "__main__":'. Also adds the argsparse call to to
acetool.py that shares cavstool code with the argument parsing.
Signed-off-by: Jyri Sarha <jyri.sarha@linux.intel.com>
Add resource_table section in linker script for i.MX8QXP and
i.MX8QM, for inter-process communication.
Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
