Add properties for describing RX and TX fifo sizes.
Also reformat some descriptions and fix the description of the
transfer-delay property which was incorrect. Since zephyr spi bufs are
not continuous, every possible Zephyr LPSPI driver must use
continuous transfer mode, for which the meaning of this delay has
nothing to do with the chip select.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Add DT property to configure the LPSPI instance to use tristated output
instead of retained output when PCS is negated.
Turn on the config on a couple boards for test coverage.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
The Atmel SAM0 SoC enable peripherals clocks in distinct places: PM and
MCLK. The old devices had defined the peripheral clock enable bit at PM.
On the newer devices this was extracted on a dedicated memory section
called Master Clock (MCLK). This change excludes the dedicated bindings
in favor of a generic approach that cover all cases.
Now the clocks properties is complemented by the atmel,assigned-clocks
property. It gives the liberty to user to customize the clock source
from a generic clock or configure the direct connections.
All peripherals drivers were reworked with the newer solution.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Rename "nxp,kinetis-dspi" compatible to "nxp,dspi" to remove the
device family from its name.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
- Add SPI driver support for RA
- RA2A1 not support slave select keeping level so disable it
in Kconfig
Signed-off-by: Tri Nguyen <tri.nguyen.wj@bp.renesas.com>
Signed-off-by: Thao Luong <thao.luong.uw@renesas.com>
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
-Update formatting and contents of index.rst for cy8ckit_062s4
-Update formatting and contents of index.rst for cy8ckit_064s0s2_4343w
-Update formatting and contents of index.rst for cy8cproto_062_4343w
-Update formatting and contents of index.rst for cy8cproto_063_ble
-Update formatting and contents of index.rst for xmc45_relax_kit
-Update formatting and contents of index.rst for xmc47_relax_kit
-Change all instances of "PSoC" to "PSOC" for infineon platforms
Signed-off-by: McAtee Maxwell <maxwell.mcatee@infineon.com>
Some instances of the FLEXSPI IP permit limiting AHB bus access so that
no memory access requests will straddle a page boundary. Add a property
to manage this setting.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Added a new driver to support SPI communication via EUSART. Since the
Silabs EFR32MG24 family SoCs have only one USART, EUSART support is
necessary for implementing SPI functionality.
Signed-off-by: Teresa Zepeda Ventura <teresa.zvent@gmail.com>
Move the `overrun-character` property from the common Nordic SPI
binding to the `spi-controller` base binding. This gives users of the
SPI interface a way to query what the default value is at compile-time,
and potentially avoid allocation of large constant buffers.
Signed-off-by: Jordan Yates <jordan@embeint.com>
... so that a clear devicetree error is reported when the pinctrl-names
property is missing, not a quite cryptic compilation error about an
undeclared PINCTRL_STATE_*_UPPER_TOKEN symbol in pinctrl.h.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add an optional DT property to specify the size of the RX/TX FIFO
implemented within the SPI core. The property name used is the same one
used by Xilinx's device tree generator.
When the FIFO is known to exist, we can use the RX FIFO occupancy register
to determine how many words can be read from the RX FIFO without checking
the RX FIFO empty flag after every read. Likewise with the TX FIFO, we can
use the FIFO size to avoid checking the FIFO full flag after every write.
This can increase overall throughput.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
Add support for a workaround required when using the Xilinx Quad SPI core
with the USE_STARTUP option, which routes the core's SPI clock to the
FPGA's dedicated CCLK pin rather than a normal I/O pin. This is typically
used when interfacing with the same SPI flash device used for FPGA
configuration. In this mode, the SPI core cannot actually take control
of the CCLK pin until a few clock cycles are issued, which would break
the first transfer issued by the core. This workaround applies a dummy
command to the connected device to ensure that the clock signal is in the
correct state for subsequent commands.
See Xilinx answer record at:
https://support.xilinx.com/s/article/52626?language=en_US
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
Some Ambiq Apollox Blue SOC (e.g. Apollo3 Blue) uses internal designed
BLEIF module which is different from the general IOM module for SPI
transceiver. The called HAL API will also be independent. This driver is
implemented for the BLEIF module usage scenarios.
Signed-off-by: Aaron Ye <aye@ambiq.com>
Some instances of the FlexSPI IP support a different clock source being
used for port B of the FlexSPI instance. Add a devicetree property and
driver support to enable configuring this property of the hardware.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Added EXMIF peripheral DTS description and bindings.
The peripheral operates as an SPI device.
Signed-off-by: Rafał Kuźnia <rafal.kuznia@nordicsemi.no>
Add support for half-duplex (3-wire) SPI operation using the Raspberry
Pi Pico PIO. To allow control of the size of the driver, including
half-duplex support is optional, under the control of Kconfig options.
The original PIO source code is also included as a reference.
Corrected 3-wire tx/rx counts.
Enable half-duplex code based on DTS configuration
Replace runtime checks with static BUILD_ASSERT()
Remove too-fussy Kconfig options
Removed PIO source per review request
Signed-off-by: Steve Boylan <stephen.boylan@beechwoods.com>
Add memory-region to nordic,nrf-spis binding. This commit aligns SPIS
shim to utilize memory-region property. This optional property enables
user to specify placement of dma buffers in memory region. It is done
by assigning to memory-region property, phandle to node with
zephyr,memory-region and mimo-sram compatible.
When memory-region property is not specified for given device, buffer
is placed in default RAM region with other data.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
This adds support for the GRLIB SPIMCTRL SPI controller used in LEON and
NOEL-V systems. SPIMCTRL can operate in two different modes: In the
default mode it allows memory-mapped read access to the flash data. When
set in the user mode, it can be used to generate SPI bus transactions.
Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
Utilize a code spell-checking tool to scan for and correct spelling errors
in all files within the dts/bindings/retained_mem, rng, serial and spi.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
The max size was determined by looking at the ARCH of the cpu. This really
comes from the ip configuration when generated. Add `max-xfer-size`
property to the devicetree.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
This cleans up the instantiation macro. DBG_COUNTER was also removed
as that appears to be unnecessary. This also allows for if it is a
serial target to be configured from the devicetree.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
add Master Inter-Data Idleness and
Master SS Idleness field. That fields
are integers.
Signed-off-by: Mustafa Abdullah Kus <mustafa.kus@sparsetechnology.com>
Add support to set SPI clock polarity (CPOL), clock phase (CPHA), and
hold-on-cs in a dts file to get rid of using related macros in spi.c driver
since each board may work on a different SPI mode rather than the default
one (based on CPOL and CPHA).
Signed-off-by: Ali Hozhabri <ali.hozhabri@st.com>
Add a new SPI shim driver for Intel SoCs. Builds upon the SEDI bare
metal SPI driver in the hal-intel module.
Co-Authored-By: Kong Li <li.kong@intel.com>
Signed-off-by: Ye Weize <weize.ye@intel.com>
These worked because edtlib allows 'pinctrl-.*' properties without
specifying them on the bindings. However, this has never been an
anounced pinctrl feature, the reference documents explicitly mention
that usage of pinctrl-device.yaml is mandatory.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Use clock control API to retrieve the module's frequency and
update the boards using it to provide the source clocks.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Initial version of Infineon CAT1 SPI Driver supporting synchronous
and asynchronous data transfer API
Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
Add fundamental feature support for RP2040 PIO SPI peripherals.
This commit implements synchronous transfer with 8-bit MSB
format. Using PIO allows any GPIO pins to be assigned the roles
of CS, CLK, MOSI, and MISO.
Optional features not implemented yet:
- Interrupt based transfer
- DMA transfer
- Slave mode
- Varying word size
- 3-wire SPI support
- LSB-first
Updated in response to review comments.
Further updates from second round of review.
Rename spi_pico_pio.c source to match zephyr/MAINTAINERS.yml
Remove unnecessary initialization code.
Resolve merge conflicts
Signed-off-by: Steve Boylan <stephen.boylan@beechwoods.com>
Add support for SPI host command backend for STM32 chips family.
Unfortunately, the current SPI API can't be used to handle the host
commands communication. The main issues are unknown command size sent
by the host(the SPI transaction sends/receives specific number of bytes)
and need to constant sending status byte(the SPI module is enabled and
disabled per transaction). Thus the SPI backend includes basic SPI STM32
driver adjusted to host command specification.
Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
