Commit Graph

26 Commits

Author SHA1 Message Date
Sven Ginka
e38f3e1c3c drivers: mdio: sy1xx add support for mdio
Add mdio support for the sensry soc sy1xx.

Signed-off-by: Sven Ginka <s.ginka@sensry.de>
2025-02-05 17:49:40 +01:00
Parthiban Veerasooran
7cfa5bf6cf drivers: mdio: lan865x: add mdio driver support
Implement lan865x mdio driver to provide interface between lan865x MAC
driver and internal PHY driver phy_microchip_t1s.c. This driver is needed
to support the driver architecture followed.

Signed-off-by: Parthiban Veerasooran <parthiban.veerasooran@microchip.com>
2025-01-16 22:45:03 +01:00
Duy Nguyen
f9705969b7 drivers: mdio: Initial support for renesas RA mdio driver
Add support for mdio driver for Renesas RA MCU series
This support utilize the r_ether_phy driver in hal renesas
to support mdio write and read function

Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
2024-12-05 07:45:19 +01:00
Yangbo Lu
4986809581 drivers: mdio: add NXP i.MX NETC MDIO driver
Added NXP i.MX NETC MDIO driver based on NXP MCUX SDK driver APIs.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2024-10-16 10:00:32 +02:00
Santosh Male
81b58ac35b dts: Added dwcxgmac dt nodes in soc dtsi file
Added XGMAC0, XGMAC1, XGMAC2 device nodes in
intel_socfpga_agilex5 dts file with default
parameter values and  default device node status
as 'disabled'.

Signed-off-by: Santosh Male <santosh.male@intel.com>
2024-09-05 17:03:05 -04:00
Fin Maaß
4436a15f34 drivers: mdio: litex: add mdio driver
add a mdio driver for litex liteeth.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-08-05 16:29:06 +02:00
Angelo Dureghello
fe29929c91 drivers: mdio: add stm32 mdio support
MDIO is part of the ETH IP, but some phy chip may need a
specific phy driver to set up certain vendor registers enabling
particular features.

Add support for stm32 mdio access.

Signed-off-by: Angelo Dureghello <adureghello@baylibre.com>
2024-05-07 09:41:46 +02:00
Declan Snyder
a7c39a2cc2 dts: bindings: Add NXP ENET QOS Bindings
Add compatibles for NXP ENET QOS drivers

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2024-04-02 21:02:25 -04:00
Andriy Gelman
d540407fc8 drivers: mdio: Add xmc4xxx mdio drivers
Add mdio drivers for xmc4xxx SoCs.

Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
2024-01-09 10:00:47 +01:00
Declan Snyder
7688e5efb1 dts: mdio-controller: Add MDC frequency property
Add a property to the mdio controller binding to describe the MDC
frequency generated by the controller.

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2023-12-19 08:51:05 +01:00
Declan Snyder
57dd852fda dts: bindings: Add NXP ENET bindings
Add bindings for compatibles related to NXP ENET IP.

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2023-11-28 14:34:02 -06:00
Manuel Argüelles
d2ea187228 drivers: mdio: add support for NXP S32 GMAC
MDIO controller is part of GMAC and it requires GMAC ethernet driver to
initialize first because it will reset the whole GMAC hw block during
initialization. Both C22 and C45 APIs are supported.

Co-authored-by: Benjamin Perseghetti <bperseghetti@rudislabs.com>
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Signed-off-by: Benjamin Perseghetti <bperseghetti@rudislabs.com>
2023-11-28 08:07:44 -06:00
Nick Kraus
5bd18886e9 sam: mdio: Fix Transfer Timeout at Initialization
Initialize the MDIO peripheral clock (normally done during GMAC
initialization) before trying any MDIO transfers, preventing startup
errors.

Signed-off-by: Nick Kraus <nick@nckraus.com>
2023-11-10 10:42:26 +01:00
Maureen Helm
d5287578fe dts: bindings: boards: Update Ethernet PHY to use reg property
Updates Ethernet PHY devicetree bindings to be more consistent with
Linux by using the standard `reg` property for the PHY address instead
of a custom `address` property. As a result, MDIO controller bindings
now require standard `#address-cells` and `#size-cells` properties.

Signed-off-by: Maureen Helm <maureen.helm@analog.com>
2023-09-29 09:47:15 +02:00
Manuel Argüelles
280ddaef4a mdio: introduce Clause 45 APIs
Add `mdio_read_c45()`/`mdio_write_c45()` APIs for Clause 45 access
and remove the `protocol` MDIO binding property so that MDIO bus
controller can support more than one protocol.

A new MDIO header is introduced with generic opcodes, MMD and
registers addresses, to be used by MDIO and PHY drivers.

Existing MDIO drivers that support both Clause 22 and Clause 45
access are migrated to the new APIs.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2023-09-28 09:33:10 +02:00
Aleksandr Senin
a1e2fdcc4d drivers: mdio: add bit-bang driver
Add MDIO driver that works through GPIO pins. This driver is
useful when a microcontroller doesn't have MDIO bus or when multiple
separate MDIO buses are required. The driver provides access to
the MDIO bus through GPIO pins for any SoC that has GPIO pin control
available.

Signed-off-by: Aleksandr Senin <al@meshium.net>
2023-09-24 08:28:10 -04:00
Georgij Cernysiov
943bc1cebc drivers: mdio: add adin2111
Adds MDIO driver. Works via exposed
ADIN2111 functions.

It is possible to access Clause 45 and 22 registers.

Due to MDIO API limitation Clause 45 access
is done using driver specific MDIO functions.

Provides API and functions for PHY driver.

Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
2023-05-26 09:50:09 -04:00
Huifeng Zhang
28ff3e1d8c drivers: eth_smsc91x: Add driver for SMSC91C111 aka LAN91C111 chip
Arm fvp_baser_aemv8r and fvp_base_revc_2xaemv8a boards are using
SMSC91C111 as their ethernet adapters.

Portions of the codes are based on FreeBSD code from its
'src/sys/dev/smc/if_smc.c' and 'src/sys/dev/smc/if_smcreg.h'.

This driver has two parts, one is the ethernet controller driver, which
is MAC layer driver. The other is the MDIO driver, which is the PHY
layer driver. Both of them are in the same source file due to that they
need to share the same reading and writing register functions and
the smsc object.

The mdio driver is needed by the existing 'phy_mii' driver, which is
a driver for the generic MII-compliant PHY.

This driver was developed under the fvp_base_revc_2xaemv8a target and
has been tested on the fvp_baser_aemv8r target.

Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
2023-04-11 11:27:05 +02:00
Manuel Arguelles
1d6452c57b drivers: mdio: add support for NXP S32 NETC EMDIO
Introduce NXP S32 NETC External MDIO controller driver. Driver supports
a single instance, as current support is based on NXP S32Z/E SoCs.

Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
2023-01-24 14:37:20 +01:00
Fabio Baltieri
eb0a524972 yamllint: indentation: fix dts/bindings/
Fix the YAML files indentation for files in dts/bindings/.

Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
2023-01-04 14:23:53 +01:00
Chris Friedt
83bea9a796 dts: bindings: clean up redundant required false attributes
DTS property attributes are (by default) not required.

Explicitly specifying `required: false` is redundant.
Perhaps a warning to that effect would be useful.

Signed-off-by: Chris Friedt <cfriedt@meta.com>
2022-11-20 13:12:44 -05:00
Grant Ramsay
113f868ddf drivers: mdio: Add ESP32 MDIO driver
The MDIO driver is required to for ESP32 Ethernet

Signed-off-by: Grant Ramsay <grant.ramsay@hotmail.com>
2022-10-01 14:51:28 -04:00
Kumar Gala
b200b9a9e0 dts: bindings: bus labels are now optional
All in tree device drivers on a bus use some form of DEVICE_DT_GET
so we no longer need to require label properties.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-07-14 09:19:35 -07:00
Gerson Fernando Budke
be387aa1c2 drivers: eth: Update sam/sam0 eth drivers to use pinctrl
This update Atmel sam and sam0 ethernet gmac and mdio drivers to use
pinctrl driver and API. It updates all boards with new pinctrl groups
format.

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
2022-03-24 15:45:37 -07:00
Arvin Farahmand
c4cb45eaac drivers: mdio: add Atmel SAM MDIO driver
MDIO driver for ATSAM platform with Ethernet.

Signed-off-by: Arvin Farahmand <arvinf@ip-logix.com>
2021-08-27 11:43:48 -04:00
Arvin Farahmand
419b103dd6 drivers: Add mdio API
This commit adds support for MDIO bus. The bus is used by Ethernet
MACs to communicate with PHYs.

Signed-off-by: Arvin Farahmand <arvinf@ip-logix.com>
2021-08-27 11:43:48 -04:00