Remove internal PHY initialization part as the phy_microchip_t1s.c
driver will do the internal PHY initialization.
Signed-off-by: Parthiban Veerasooran <parthiban.veerasooran@microchip.com>
Add support for LAN8650/1 Rev.B1. As per the latest configuration note
AN1760 released (Revision F (DS60001760G - June 2024)) for Rev.B0 is also
applicable for Rev.B1. Refer hardware revisions list in the latest AN1760
Revision F (DS60001760G - June 2024).
https://www.microchip.com/en-us/application-notes/an1760
Signed-off-by: Parthiban Veerasooran <parthiban.veerasooran@microchip.com>
This implements to generate the MAC address of the device UUID.
The UUID is hashed to reduce the size to 3 bytes.
Ideas taken from eth_nxp_enet.c
Adding dependencies on: HWInfo and CRC
Signed-off-by: Adib Taraben <theadib@gmail.com>
This PR adds support for LAN9250 spi ethernet controller.
This driver is tested on the Mikroe ETH Click 3
https://www.mikroe.com/eth-3-click
Signed-off-by: Mario Paja <mariopaja@hotmail.com>
New driver for Davicom DM8806 PHY. Driver is using standar mdio API
to manage the DM8806 switch controller. Register access needs the
PHY addres or switch address to be one of five possible values, since
DM8806 has built-in five PHY's. These values should be defined in the
application .dts file. One DM8806 ethernet port must corresponds with
one ethernet PHY node with two properties for ethernet port: one for
PHY address and one for switch address - <reg> for register access from
Internal PHY Register area and <reg-switch> for register access from
Switch Per-Port Registers area. Device tree example below:
example device-tree:
dm8806_phy: ethernet-phy@0 {
reg = <2>;
reg-switch = <8>;
compatible = "davicom,dm8806-phy";
status = "okay";
davicom,interface-type = "rmii";
reset-gpio = <&gpiod 2 GPIO_ACTIVE_LOW>;
interrupt-gpio = <&gpioc 1 GPIO_ACTIVE_HIGH>;
};
Signed-off-by: Robert Slawinski <robert.slawinski1@gmail.com>
This commit is to enable Ethernet drivers support on Renesas RA
MCU, first target support is the Renesas RA8 series
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
Add stm32h7 ethernet compatible "st,stm32h7-ethernet",
used also for stm32h5.
Signed-off-by: IBEN EL HADJ MESSAOUD Marwa <marwa.ibenelhadjmessaoud-ext@st.com>
Added XGMAC0, XGMAC1, XGMAC2 device nodes in
intel_socfpga_agilex5 dts file with default
parameter values and default device node status
as 'disabled'.
Signed-off-by: Santosh Male <santosh.male@intel.com>
Rename it from litex,eth to litex,liteeth
to reflect the new name of the driver.
Zero got removed from the litex
ethernet compatible, as it now supports
multiple instances.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
nxp,unique-mac actually is not meant to be universally
unique, the LAA bit should therefore be set, and fix the
description of the property in the binding to clarify
the intended usage of this property.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Fix KSZ8081 binding properties:
- reset-gpios and interrupt-gpios are generally standard
properties and therefore should not be using a special name
- mc, is not the correct vendor prefix for microchip
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Add driver for Realtek RTL8211F 10/100/1000M ethernet PHY.
This driver implements vendor specific behaviour like
detecting link state change by GPIO interrupt, which is not
present in the generic MII driver.
Fixes: #66348
Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com>
- Added nxp,enet1g compatible to distinguish between ENET (nxp,enet)
and ENET_1G (nxp,enet1g) peripherals within the same driver.
- Added config ETH_NXP_ENET_1G to enable 1G mode of operation on ENET_1G.
- Support RGMII mode of connection between MDIO and PHY to be
able to work with ENET_1G peripheral and support 1000M speed.
- Removed performing of PHY reset before configuring link - it is
not desirable for RTL8211F PHY connected to ENET_1G on RT1170.
Reset of other PHYs can be performed by PHY driver itself if required.
Fixes: #66348
Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com>
Add option for RGMII connection type between the MAC and the PHY
device into the ethernet controller binding.
Fixes: #66348
Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com>
Add support for similar adin1100 phy, boath are 10Base-T1L,
only difference is that adin1100 connects through r/mii.
Signed-off-by: Angelo Dureghello <angelo@kernel-space.org>
The MAC address macros are ridiculous in this driver.
Rewrite to be simpler and use eth.h common function.
Also, clarify the mac address generation on the DT overlays.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Remove ethernet-fixed-link binding as it is redundant with the
phy bindings. Clearly, ethernet does not work without the L1
layer, which is a phy device, or an integrated mac/phy device,
and all of these things should be described properly in DT.
The schema did not even come with a compatible, meaning nodelabels
were hardcoded into the drivers, which is unacceptable.
- Remove the binding file for ethernet-fixed-link.yaml.
- Remove fixed link functionality from the nxp s32 gmac driver.
Since this functionality is already covered by the phy support,
it is redundant.
- Remove fixed link include from the s32 gmac binding.
- Remove fixed link include from the nuvoton numaker binding.
As far as I can tell the corresonding driver does not even
use it anyways, and I did not find any board with this device
that describes a "fixed link".
- Move the definition into the nxp,kinetis-ethernet binding
as the eth_mcux driver, which is already being deprecated,
does use this, contain the debt to the legacy driver.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Byte value written to the device's
ERXFCON: ETHERNET RECEIVE FILTER CONTROL REGISTER
Sets the devices receive packet filter, optional. If not set
in device tree previous hard coded value`0xA3` is used.
Uni, multi and broadcast packets with valid CRC are accepted.
Signed-off-by: Dean Sellers <dsellers@evos.com.au>
Add Open Alliance spi protocol support.
Open Alliance is a chunk-based SPI protocol, based on sending
over SPI an ethernet frame divided in smaller chunks, using a
specific 32-bit header for each chunk transferred. All chunks
can be sent or received by a single dma transfer.
Default mode is set to Open Alliance SPI without protection,
since the adin2111 dev. board comes shipped this way.
Tested:
- Open Alliance SPI, no protection (default board shipped)
- Open Alliance SPI, protection
- Generic SPI, no crc
- Generic SPI, with crc8
Signed-off-by: Angelo Dureghello <adureghello@baylibre.com>
drivers: eth: phy: tja1103: Handle link change
These changes enable -
TJA1103 driver to gracefully handle Link connect or disconnect events
between Ethernet PHY and its link partner and notify it to the
upper network layers
Signed-off-by: Sumit Batra <sumit.batra@nxp.com>
Utilize a code spell-checking tool to scan for and correct spelling errors
in all files within the dts/bindings/ethernet, gpio, i2c and
interrupt-controller.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
- PHY can be set up as rmii but still use 25 MHz MDC, add DT property
value for this case
- Fix KSZ8081 driver spamming phy status in debug level logging,
and fix some other state/logging logic
- Fix PHY driver not rescheduling monitor work if first configuration
fails, change code path to use goto for errors
- Handle case where some phys are not using the gpio pins in phy driver
Make GPIO properties of ksz8081 phy optional since these hardware pins
may be unused on some boards
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
In case of boards where REF_CLK signal is not connected
to the GPIO0 by default add the possibility to use
the optional GPIO16/GPIO17 as a REF CLK source.
Signed-off-by: Bartosz Bilas <bartosz.bilas@hotmail.com>
Add Driver for KSZ8081 Ethernet PHY. The Generic MII Driver
is not sufficient to use for this PHY chip which has special
vendor implemented behaviors.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Add a property to the ethernet controller binding
indicating what type of connection the MAC has with
the PHY device.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Adds the tja1103 enet phy for setting phy options on the mr_canhubk3.
Co-authored-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Co-authored-by: Peter van der Perk <peter.vanderperk@nxp.com>
Signed-off-by: Benjamin Perseghetti <bperseghetti@rudislabs.com>
This patch set provides support for T1S ethernet device - LAN8651.
For SPI communication the implementation of Open Alliance TC6
specification is used.
The driver implementation focuses mostly on reducing memory footprint,
as the used SoC (STM32G491) for development has only 32 KiB RAM in total.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Updates Ethernet PHY devicetree bindings to be more consistent with
Linux by using the standard `reg` property for the PHY address instead
of a custom `address` property. As a result, MDIO controller bindings
now require standard `#address-cells` and `#size-cells` properties.
Signed-off-by: Maureen Helm <maureen.helm@analog.com>
Some Ethernet PHYs used the devicetree node name `phy`, while others
used `ethernet-phy`. Be consistent and use `ethernet-phy` throughout.
Signed-off-by: Maureen Helm <maureen.helm@analog.com>
