The Atmel SAM0 SoC enable peripherals clocks in distinct places: PM and
MCLK. The old devices had defined the peripheral clock enable bit at PM.
On the newer devices this was extracted on a dedicated memory section
called Master Clock (MCLK). This change excludes the dedicated bindings
in favor of a generic approach that cover all cases.
Now the clocks properties is complemented by the atmel,assigned-clocks
property. It gives the liberty to user to customize the clock source
from a generic clock or configure the direct connections.
All peripherals drivers were reworked with the newer solution.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Rename the following properties in binding and overlay:
-- primary_source => primary-source
-- secondary_source => secondary-source
-- filter_count => filter-count
-- filter_period => filter-period
Signed-off-by: James Roy <rruuaanng@outlook.com>
This is a squash of all the groundwork needed to
get a functioning driver for the DS3231 with the RTC API.
Signed-off-by: Gergo Vari <work@gergovari.com>
A few bindings in the timer directory (for kernel timing sources) were
being used for counters (which can have alarms set, and have a distinct
API). Move these bindings to the counters directory.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
- boards: renesas: Add support for agt.
- drivers: counter: Add support for counter driver use agt
- dts: arm: Add support for agt.
- dts: bindings: Add support for agt counter driver.
- soc: renesas: Add support for agt counter driver.
- samples: drivers: counter: alarm: Add support for RA8
This is initial support with only basic functionality for counter
operation on Zephyr using AGT hardware, current support for
count source is limited to LOCO and PCLKB, other count source
like underflow signal external pin or AGTIO from another AGT
channel will be added in later support
Signed-off-by: Ha Nguyen <ha.nguyen.fz@bp.renesas.com>
Signed-off-by: Thao Luong <thao.luong.uw@renesas.com>
Signed-off-by: Duy Phuong Hoang. Nguyen <duy.nguyen.xa@renesas.com>
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
Updated the counter_mcux_lptmr driver to support multiple
instances of the lptmr peripheral. Also added a new
binding property to identify if the user is using
counter-mode or pulse mode. since we were previously using the
prescaler value to check this which could be wrong
if used as a division value for getting the freq.
Added a property that allows the user to decide
what the counter value in lptmr should be divided by.
Cleaned up INIT macro for lptmr.
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
Updated the clocks that get initialized for the MCXN947
when using the LPTMR. The LPTMR allows the user to select
and Input clock, however said input clock must be
initialized before the user can select it.
Update description for clk-source in binding file.
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
Added a single instance lptmr node on the
mcxn947 soc dts. Updated counter lptmr to
have max value property.
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
Rename nxp,kinetis-lptmr compat to nxp,lptmr.
Because of concerns over breaking downstream users,
keep support for the old compatible temporarily and
make it clear it should be changed.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
The RTC subsystem in espressif's SOCs, among other tasks
is responsible for clock selection for CPU and for low
power domain clocks such as RTC_SLOW and RTC_FAST.
This commit allows for proper clock source and rate
selection for CPU, using the espressif,riscv and
espressif,xtensa-lx6/7 bindings.
It also enables clock selection for RTC_FAST and RTC_SLOW,
that impacts some peripherals, such as rtc_timer.
Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
Include reset device binding in some of the NXP LPC
IP bindings to be able to add the resets property.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Updating the nxp,pit driver to support mutliple
channels. Updating the dts and board overlays
to account for the changes.
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
A 1KHz counter is also available inside the NXP LPC RTC
block. Add a binding to support that counter.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Add binding for nxp,mrt and nxp,mrt-channel. MRT is
NXP multirate timer, a simple timer with multiple
independent channels.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Add initial version of Infineon CAT1 counter driver
Add initial version of binding file for Infineon
Add counters to psco6 dtsi
Add external trigger pin that runs counter
Signed-off-by: Pavlo Havrylyuk <pavlo.havrylyuk@infineon.com>
Added RTC driver that supports Motorola MC146818B
Enabled RTC set/get time and alarm, alarm callback
and update callback.
Counter and RTC uses same hardware in case of
Motorola MC146818, so they can't be used at a time.
Updated stand-alone mc146818 counter dts instances
to support rtc and counter with same compatible
string of "motorola,mc146818" on ia32, atom,
apollo_lake, elhart_lake and raptor_lake platforms.
Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
DTS property attributes are (by default) not required.
Explicitly specifying `required: false` is redundant.
Perhaps a warning to that effect would be useful.
Signed-off-by: Chris Friedt <cfriedt@meta.com>
We have drivers for "nxp,lpc-rtc" and "zephyr,native-posix-counter"
devicetree compatibles, however we had no bindings for them. Add
simple bindings
Signed-off-by: Kumar Gala <galak@kernel.org>
All in tree device drivers use some form of DEVICE_DT_GET
so we no longer need to require label properties.
Signed-off-by: Kumar Gala <galak@kernel.org>
- adds properties 'group', 'index' and 'prescaler'.
- updates board's dts to include those properties.
Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
Add DTS binding for Motorola MC146818 compatible Real Time Clock.
This is being used for the RTC/CMOS timer on x86 PC-compatible
platforms.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
