Currently the interrupt number of the ADC node is duplicated
with other node on several RA soc. This commit aim to
resolve this issue.
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
- Add device tree support for Renesas r7fa4m1ab3cfp with basic
gpio, clock control, sci, counter drivers, adc
- Add clock-frequency in renesas,ra-cgc-pclk binding to use the
clock frequency for iclk
Signed-off-by: Tran Van Quy <quy.tran.pz@renesas.com>
- Remove redundant node adc1 on ra4-cm4-common due to unsupported
- Update interrupt number for spi1
Signed-off-by: Tran Van Quy <quy.tran.pz@renesas.com>
- Update the overlapping irq number between port_irq4 and spi1
- Remove irq number for sci9 as it exceeds the limit (32 irq numbers)
Now users will define the irq numbers themselves
Signed-off-by: Quy Tran <quy.tran.pz@renesas.com>
- Add Flash HP support for ra6-cm4, ra6-cm33, ra4-cm33 (except
r7fa4w1ad2cng)
- Add config to set the minimal size of data which can be written
for RA4E2, RA4M2, RA4M3, RA6E1, RA6E2, RA6M1, RA6M2, RA6M3, RA6M4,
RA6M5
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
Signed-off-by: Phi Tran <phi.tran.jg@bp.renesas.com>
- Bring macro defined of RA8 in flash_hp_ra.h to device tree
- Change to use irq_lock instead of semaphore for code flash
- Modify and add conditions to check and make decision to perform
action at last block.
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
Signed-off-by: Tran Van Quy <quy.tran.pz@renesas.com>
Add dts node to support for gpio interrupt on Renesas RA SoC
- Add external interrupt node
- Add gpio interrupt pins
Signed-off-by: The Nguyen <the.nguyen.yf@renesas.com>
Move ioport6, ioport7, ioport8 to r7fa6m4ax due to it is common
part of RA6M4
Impacted file:
- dts/arm/renesas/ra/ra6/r7fa6m4ax.dtsi
- dts/arm/renesas/ra/ra6/r7fa6m4af3cfb.dtsi
Signed-off-by: The Nguyen <the.nguyen.yf@renesas.com>
- Add "channel-available-mask" property in ADC node
to detect which channels are available to use
- Add "add-average-count" property in ADC node to chose
number of count of the addition or average mode
- Change the source code of ADC to match with 2 new properties.
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
This is the initial commit to support UART driver for Renesas RZ/G3S.
The driver only implements polling API for minimal support.
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
Signed-off-by: Binh Nguyen <binh.nguyen.xw@renesas.com>
This is the initial commit to support pinctrl driver for Renesas RZ/G3S
Signed-off-by: Quang Le <quang.le.eb@bp.renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
This adds minimal support for a new SoC Renesas RZ/G3S
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
Signed-off-by: Binh Nguyen <binh.nguyen.xw@renesas.com>
This commit is to enable Ethernet drivers support on Renesas RA
MCU, first target support is the Renesas RA8 series
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
The new update of clock device tree make the pll p q r clock
source cannot be choose by other node
This fix add 1 new dts binding for pll out p q r out line
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
- Modify the macro in source code AGT to get the right data from
device tree
- Modify name of agt node
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
Additional IO ports (6,7 and 8) are availble on the r7fa6m4af3cfb
variant of the RA6M4 Microcontroller.
Signed-off-by: Ian Morris <ian.d.morris@outlook.com>
