A specific section of the flash on the SiWx917 is reserved for the
Network co-processor (NWP). This zone needs to be delimited in order to
not overwrite it. We then need to use "code-partition" to provide Zephyr
the application code flash location.
Co-authored-by: Martin Hoff <martin.hoff@silabs.com>
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Report DMA configuration in the board definitions.
Note the addresses of the DMA buffers are hardcoded in the HAL. So,
these areas have to be declared in the linker file.
Co-authored-by: Sai Santhosh Malae <santhosh.malae@silabs.com>
Signed-off-by: Sai Santhosh Malae <santhosh.malae@silabs.com>
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Introduce minimal support for Silicon Labs SiWx91x family. SiWx91x
provide many device and especially Bluetooth and Wifi connectivity. This
patch prepare Zephyr to receive further drivers.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Currently the interrupt number of the ADC node is duplicated
with other node on several RA soc. This commit aim to
resolve this issue.
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
The infineon xmc4xxx series has two ways to access flash: one is the
cacheable address space at 0x8000000 which may return pre-fetched/cached
data to reduce flash access latency, the second is non-cached space
at 0xc000000 which is mainly used for write and erase operations.
Currently the LMA is set to the non-cachable address which is not
efficient for executing in place (XIP). Instead use the cacheable
address for the LMA.
Even though the cacheable address is used for the LMA, the J-Link
probe properly figures that it has to use non-cached space for erasing
and writing to flash.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
Add properties to differentiate the timer counter operating modes. This
properties are necessary to spetialize the driver to be used as a normal
16/32-bit counter or to provide the clock/calendar functions.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Improve the silabs ldma driver to support P2M and M2P transfer. It also
adds signal binding to support source request binding in the dts.
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
Added SOC DTS for MCXW72
Adding BLE required info to MCXW72 dtsi
Signed-off-by: Yassine El Aissaoui <yassine.elaissaoui@nxp.com>
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
- Add device tree support for Renesas r7fa4m1ab3cfp with basic
gpio, clock control, sci, counter drivers, adc
- Add clock-frequency in renesas,ra-cgc-pclk binding to use the
clock frequency for iclk
Signed-off-by: Tran Van Quy <quy.tran.pz@renesas.com>
- Remove redundant node adc1 on ra4-cm4-common due to unsupported
- Update interrupt number for spi1
Signed-off-by: Tran Van Quy <quy.tran.pz@renesas.com>
Defines an acmp node for xg21, xg23, xg24, xg27 and xg29
parts, which are all compatible with the silabs,acmp
binding.
Signed-off-by: Christian Galante <christian.galante@silabs.com>
Add properties for describing RX and TX fifo sizes.
Also reformat some descriptions and fix the description of the
transfer-delay property which was incorrect. Since zephyr spi bufs are
not continuous, every possible Zephyr LPSPI driver must use
continuous transfer mode, for which the meaning of this delay has
nothing to do with the chip select.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
There is no such thing as associating a compatible to a child binding
so remove this from the nxp,dmic binding definition and devicetree files
that incorrectly set one.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
The GPIO peripheral on Silabs Series 2 devices is responsible for
allocating analog buses to analog peripherals. Enable support for
this in the pinctrl driver. Since these bus allocations are not
digital pins, introduce a new property silabs,analog-bus for this
purpose.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
- Update the overlapping irq number between port_irq4 and spi1
- Remove irq number for sci9 as it exceeds the limit (32 irq numbers)
Now users will define the irq numbers themselves
Signed-off-by: Quy Tran <quy.tran.pz@renesas.com>
