Add Clock Control driver support for Renesas RZ/G3S
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
Rename the following properties in bindings and DTS:
-- freqs_mhz => freqs-mhz
-- cg_reg => cg-reg
-- pll_ctrl_reg => pll-ctrl-reg
Signed-off-by: James Roy <rruuaanng@outlook.com>
This driver allow to use Zephyr native IP stack or the IP stack provided
by HAL / WiseConnect.
The WiseConnect implementation may take advantage of the specific
features provided by the 917 (power consumption, speed,
validation...).
Some notable features are not available with this interface:
- It seems Zephyr does not provide API to offload multicast membership
management. User should be to directly call WiseConnect APIs
- Support for ICMP frames is difficult. Note that WiseConnect
automatically answer to ping request. It is just not possible to
send ping requests and receive ping responses.
- Zephyr and WiseConnect both support TLS offloading. However this
patch does not implement it.
- Reentrancy in the WiseConnect side is uncertain.
This implementation has been tested with samples/net/wifi/ (which relies
on subsys/net/lib/shell).
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Driver was tested with a custom application which enabled the BT_SHELL.
Basic functionalities were verified:
- Scanning
- Advertising
- Connecting
Configuration needed for the test:
- CONFIG_BT=y
- CONFIG_BT_PERIPHERAL=y
- CONFIG_BT_CENTRAL=y
- CONFIG_BT_SHELL=y
- CONFIG_SHELL=y
Co-authored-by: Tibor Laczko <tibor.laczko@silabs.com>
Signed-off-by: Tibor Laczko <tibor.laczko@silabs.com>
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
A specific section of the flash on the SiWx917 is reserved for the
Network co-processor (NWP). This zone needs to be delimited in order to
not overwrite it. We then need to use "code-partition" to provide Zephyr
the application code flash location.
Co-authored-by: Martin Hoff <martin.hoff@silabs.com>
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Report DMA configuration in the board definitions.
Note the addresses of the DMA buffers are hardcoded in the HAL. So,
these areas have to be declared in the linker file.
Co-authored-by: Sai Santhosh Malae <santhosh.malae@silabs.com>
Signed-off-by: Sai Santhosh Malae <santhosh.malae@silabs.com>
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Implement DMA driver for siwx917 using UDMA peripheral. For now,
Scatter/Gather DMA is not yet supported.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Support for random number generator is required for most of the
cryptographic operations, including support for WiFi and TLS.
This driver has been tested with tests/drivers/entropy:
*** Booting Zephyr OS build v3.7.0-4339-g1ec5ce05f9f8 ***
Running TESTSUITE entropy_api
===================================================================
START - test_entropy_get_entropy
random device is 0x8217298, name is rng@45090000
0x93
0x3e
0xf1
0x68
0xd4
0x22
0xbf
0x4d
0xad
PASS - test_entropy_get_entropy in 0.012 seconds
===================================================================
TESTSUITE entropy_api succeeded
------ TESTSUITE SUMMARY START ------
SUITE PASS - 100.00% [entropy_api]: pass = 1, fail = 0, skip = 0 ...
- PASS - [entropy_api.test_entropy_get_entropy] duration = 0.01 ...
------ TESTSUITE SUMMARY END ------
===================================================================
RunID: d1547c805699201af769cb01331efcce
PROJECT EXECUTION SUCCESSFUL
Co-authored-by: Tibor Laczko <tibor.laczko@silabs.com>
Signed-off-by: Tibor Laczko <tibor.laczko@silabs.com>
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
This device is included on Silabs SiWx91x series. The current driver is
able to manage "High Power" and "Ultra Low Power" pins.
Co-authored-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Introduce minimal support for Silicon Labs SiWx91x family. SiWx91x
provide many device and especially Bluetooth and Wifi connectivity. This
patch prepare Zephyr to receive further drivers.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
This driver is mostly the initial seed for further implementation of a
real clock driver.
It doesn't allow the user to choose the clock source for the various
peripherals. The driver hardcodes some sane values.
Note that for now, the driver snps,designware-i2c does not support
"clocks" attribute. So this patch hardcode the clock configuration in
the init of the clock driver.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
NXP i.MX NETC is a TSN capable Ethernet IP. It may support
ENETC MACs, or/and multiple ports switch.
The ENETC MAC was handled by eth_nxp_imx_netc driver.
This DSA driver is to support NETC switch device.
Current driver supports DSA with limitation that only switch
function is available without management via DSA master port.
DSA master port support is TODO work.
Take i.MX RT1180 NETC hardware as an example.
+--------+ +--------+
| ENETC1 | | ENETC0 |
| | | |
| Pseudo | | 1G |
| MAC | | MAC |
+--------+ +--------+
| zero copy interface |
+-------------- +--------+----------------+ |
| | Pseudo | | |
| | MAC | | |
| | | | |
| | Port 4 | | |
| +--------+ | |
| SWITCH CORE | |
+--------+ +--------+ +--------+ +--------+ |
| Port 0 | | Port 1 | | Port 2 | | Port 3 | |
| | | | | | | | |
| 1G | | 1G | | 1G | | 1G | |
| MAC | | MAC | | MAC | | MAC | |
+--------+-+--------+-+--------+-+--------+ |
| | | | |
NETC External Interfaces (4 switch ports, 1 end-point port)
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Add new item ulps_control in binding. If the MIPI DSI on the SoC support
ULPS, and user set the bus to enter ULPS after transfer in mipi_dsi_msg,
driver will set the bus to enter ULPS.
Signed-off-by: Kate Wang <yumeng.wang@nxp.com>
Currently the interrupt number of the ADC node is duplicated
with other node on several RA soc. This commit aim to
resolve this issue.
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
The infineon xmc4xxx series has two ways to access flash: one is the
cacheable address space at 0x8000000 which may return pre-fetched/cached
data to reduce flash access latency, the second is non-cached space
at 0xc000000 which is mainly used for write and erase operations.
Currently the LMA is set to the non-cachable address which is not
efficient for executing in place (XIP). Instead use the cacheable
address for the LMA.
Even though the cacheable address is used for the LMA, the J-Link
probe properly figures that it has to use non-cached space for erasing
and writing to flash.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
Introduce new DAI driver used for NXP's PDM MICFIL IP.
This block implements required digital interface to provide
a 24-bits audio signal from a PDM microphone bitstream in a configurable
output sampling rate.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
