Rename _XFR_.*BITS and _WRITE_ONLY_ABSENT according to MISRA-C standard
rules 21.1 and 21.2 (Zephyr rules 121 and 122). For details see Zephyr
coding guidelines in table "Main rules".
Signed-off-by: Stephan Linz <linz@li-pro.net>
Use a string for the xfr-min-bits property over an integer value, as this
significantly improves the readability of the MIPI DBI SPI device binding.
Signed-off-by: Stephan Linz <linz@li-pro.net>
For a 16-bit data bus, "DT_INST_PROP_LEN(n, data_gpios)" returns 16
which is equals "MIPI_DBI_MAX_DATA_BUS_WIDTH(16)".
As a result, the assertion will always be triggered.
Use a "<=" condition for the assertion instead.
Signed-off-by: Hua Zheng <writeforever@foxmail.com>
Add support for the mipi_dbi_configure_te API within the NXP LCDIC
peripheral. Also, remove a redundant code patch in the write_command
function that was previously used to determine when the display driver
was writing to graphics RAM, as these writes should now be performed
using the mipi_dbi_write_display API.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Extends the MIPI DBI SPI driver class for operating mode C4, SPI 4-wire,
with 16 write clocks to send one or multiple byte for commands. Generic
data (e.g. GRAM) aligned to 16-bit are passed through and stuffed with
bytes if required.
Signed-off-by: Stephan Linz <linz@li-pro.net>
The more complex the SPI transfer algorithms become, the more
confusing the current implementation of the SPI write function
becomes. Furthermore, if further as yet unknown MIPI DBI modes
are to be supported, the scope of this implementation would
increase dramatically. With the splitting now introduced, the
existing SPI transfer algorithms are moved to individual
auxiliary functions and the SPI write function only focus on
the decision of the respective MIPI DBI mode and the device
lock/unlock.
Signed-off-by: Stephan Linz <linz@li-pro.net>
The more complex the SPI transfer algorithms become, the more
confusing the current implementation of the SPI command read
function becomes. Furthermore, if further as yet unknown MIPI
DBI modes are to be supported, the scope of this implementation
would increase dramatically. With the splitting now introduced,
the existing SPI transfer algorithms are moved to individual
auxiliary functions and the SPI read function only focus on
the decision of the respective MIPI DBI mode and the device
lock/unlock.
Signed-off-by: Stephan Linz <linz@li-pro.net>
Reset pulse count can be up to 512 before we would be unable to support
it using the peripheral. Use a uint32_t for the count, so that even long
reset pulses will still be calculated correctly. Add code to warn about
reset pulse requests that are too long.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The NXP LCDIC peripheral contains two internal timers, with configurable
periods. These times are used to determine delays within the peripheral,
such as the reset and tearing enable signal delays. Allow these periods
to be set within the devicetree for the peripheral.
Raise the period where required for display drivers that need a value
other than the reset setting
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Obviously, everyone knows that there are 8 bits per byte, so
there isn't a lot of magic happening, per se, but it's also
helpful to clearly denote where the magic number 8 is referring
to the number of bits in a byte.
Occasionally, 8 will refer to a field size or offset in a
structure, MMR, or word. Occasionally, the number 8 will refer
to the number of bytes in a 64-bit value (which should probably
be replaced with `sizeof(uint64_t)`).
For converting bits to bytes, or vice-versa, let's use
`BITS_PER_BYTE` for clarity (or other appropriate `BITS_PER_*`
macros).
Signed-off-by: Chris Friedt <cfriedt@tenstorrent.com>
The Drivers using Pinctrl should be turning Pinctrl on
this should not be the responsibility of the board. This
commit removes CONFIG_PINCTRL from the boards side for nxp boards.
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
DT_REG_ADDR now generates an unsigned string terminated with U
which doesn't match the way the macros is used in a CONCAT
to build a FMC_BANK1_(1/2/3) define that is defined in hal.
`DT_REG_ADDR_RAW` should now be used to get the RAW FMC bank index
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
Enable support for 8 bit 8080 mode in the NXP LCDIC driver. Support
for programming the minimum duration of the write active/inactive signal
is also added, since this will be required to support high display
clocks in 8080 mode.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Introduce GPIO-based driver for MIPI DBI class that allows MIPI DBI
type A and B displays to be used on general platforms.
Since each data pin GPIO can be selected individually, the bus pins are
set in a loop, which has a significant negative impact on performance.
When using 8-bit mode and all the data GPIO pins are on the same port,
a look-up table is generated to set the whole port at once as a
performance optimization. This creates a ROM overhead of about 1 kiB.
Tested 8-bit 8080 mode with ILI9486 display on nRF52840-DK board.
Signed-off-by: Stefan Gloor <code@stefan-gloor.ch>
The reset function uses uint32_t as its 2nd parameter, which leads to the
following compiler warning.
zephyr/drivers/mipi_dbi/mipi_dbi_stm32_fmc.c:176:18: warning:
initialization of 'int (*)(const struct device *, k_timeout_t)' from
incompatible pointer type 'int (*)(const struct device *, uint32_t)'
{aka 'int (*)(const struct device *, unsigned int)'}
[-Wincompatible-pointer-types]
176 | .reset = mipi_dbi_stm32_fmc_reset,
| ^~~~~~~~~~~~~~~~~~~~~~~~
When you look at similar drivers,
/drivers/mipi_dbi/mipi_dbi_smartbond.c#L126
/drivers/mipi_dbi/mipi_dbi_nxp_lcdic.c#L561
you notice they use k_timeout_t.
So the whole fix is to correct the type.
Signed-off-by: Thorsten Spätling <thorsten.spaetling@vierling.de>
Reset delay was not being calculated correctly in lcdic driver, the
ticks field needs to be accessed directly within the timeout structure
to calculate the correct delay time
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add support for using the stm32 fmc to interact with a display
controller, using Intel 8080 protocol with a 16 bits parallel bus.
Signed-off-by: Miguel Gazquez <miguel.gazquez@bootlin.com>
Calling k_msleep() leads to a int64_t division, causing udivdi3 and
similar to be linked in.
Keep the outer API the same, but switch to k_timeout_t before passing
to the inner API. This saves 1916 B of ROM.
Signed-off-by: Michael Hope <mlhx@google.com>
Constify the config and reorder the data fields for better packing.
This reduces the RAM usage of `mipi_dbi_spi` by 20 bytes.
Signed-off-by: Michael Hope <mlhx@google.com>
This commit should deal with fixing
various issues on the board's dts
overlay files:
1. PSRAM node was not enabled when
display buffers were stored in
psram and thus, raising linker
error (overflow memory section).
2. Remove MIPI DBI read operations
for the MIPI DBI driver. This is
because not all drivers support
read and most of the cases it does
not have any practical usage.
In addition, this might trigger
conflicts with SPI sensors.
If needed, users should explicitly
enable read operations by defining
an SPI device taking into consideration
conflicts with SPI devices connected
to the SPI bus.
3. Remove enabling the DMA driver.
It should be enabled by default.
Signed-off-by: Ioannis Karachalios <ioannis.karachalios.px@renesas.com>
Removed PM device runtime support from drivers in PD_SYS domain.
Update the rest device drivers to call pm_device_runtime_get/put()
functions when CONFIG_PM_DEVICE_RUNTIME is enabled.
Signed-off-by: Ioannis Damigos <ioannis.damigos.uj@renesas.com>
This commit should optimize the way the device is allowed
to enter the suspended state. Instead of returning a PM
error code to abort the PM process, the standby power state
is constrained as long as the device is not allowed to enter
suspension. With that approach, acquiring PD_SYS is not needed
when in PM device runtime mode.
Signed-off-by: Ioannis Karachalios <ioannis.karachalios.px@renesas.com>
Require that SPI config within the MIPI DBI API use 9 bit SPI mode, as 3
wire spi requires the command/data bit be packed into the start of the
SPI packet.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The power rail of a peripheral block should always be
acquired/released before/after its employment even if
it's known that it should already be up and running.
Signed-off-by: Ioannis Karachalios <ioannis.karachalios.px@renesas.com>
This commit should add all the functionality needed for the MIPI DBI
driver to work when PM is enabled.
Signed-off-by: Ioannis Karachalios <ioannis.karachalios.px@renesas.com>
Some SPI based displays expect the ability to lock the SPI bus after a
transaction completes, or to hold CS low. In order to accommodate this
within the MIPI DBI layer, add the mipi_dbi_release API, which allows
SPI displays to hold then release the SPI bus used by the MIPI
abstraction layer.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Introduce NXP LCDIC driver using MIPI DBI class. This peripheral
supports 8080 and SPI 3/4 wire mode, although only SPI 4 wire support is
currently implemented. The driver supports DMA and interrupt driven
transfers.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Taking a spinlock will result in interrupts being blocked in the MIPI
DBI driver, which is not desired behavior while issuing SPI transfers,
since the driver may use interrupts to drive the transfer
Fixes#68815
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Change reset pin polarity for MIPI DBI SPI controller, so that the board
devicetree is responsible for setting the GPIO to active low, and the
driver always sets the pin to a logic 1 to reset the display.
Fixes#68562
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add cleanups to pin presence checks within the mipi_dbi SPI driver.
The cleanups now verify that GPIO and RESET pin devices are ready,
if they are present for the device instance.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
SPI controllers can easily implement MIPI DBI mode C, with the help of
GPIO pins for the reset and command/data signals. Introduce a MIPI DBI
compliant SPI driver, which emulates MIPI DBI mode C (SPI 3 and 4 wire).
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Introduce MIPI DBI driver class. MIPI DBI devices encompass several
interface types. All interfaces have a data/command, reset, chip select,
and tearing effect signal
Beyond this, MIPI DBI operates in 3 modes:
Mode A- 16/8 data pins, one clock pin, one read/write pin. Similar to
Motorola type 6800 bus
Mode B- 16/8 data pins, one read/write pin. Similar to Intel 8080 bus
Mode C- 1 data output pin, 1 data input pin, one clock pin.
Implementable using SPI peripheral, or MIPI-DBI specific controller.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
