Adds a basic driver for the STM32WB0 flash controller (read/erase/write).
Extended operations are not supported by this driver.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
Add missing braces to comply with MISRA C:2012 Rule 15.6 and
also following Zephyr's style guideline.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Add condition for KConfig Renesas FSP hal module
Move the DUAL_BANK_MODE from SOC to flash driver KCONFIG
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
Remove all entries that as not being used.
This also update hal to re-enable warning flags
as such as -Wno-unused-variable.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Wait until the erase operation triggered by `qspi_erase` completes
before returning. This aligns with the behaviour of other flash drivers
like `spi_nor` and `soc_flash_nrf`.
A delay is added to the `qspi_wait_while_writing` to prevent the check
from monopolising the CPU.
Signed-off-by: Jordan Yates <jordan@embeint.com>
Move some STM32 drivers related Kconfig symbols from `config`
to `menuconfig` when driver options depends on these symbols.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Select PINCTRL subsystem by drivers which require it.
Prevent the need from enabling this symbol at board or soc level.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Automatically handle device runtime PM for all flash API calls.
Asynchronously release the device after a small delay to minimise power
state transitions under multiple sequential API calls (e.g. NVS).
Signed-off-by: Jordan Yates <jordan@embeint.com>
Remove `SPI_NOR_IDLE_IN_DPD` to simplify the possible transition states
in the `spi_nor` driver. This option was originally added 5 years ago
when device runtime PM was in a much less mature state.
I do not believe having a separate power management implementation for
this one in-tree driver is in the interests of the project.
The behaviour of `SPI_NOR_IDLE_IN_DPD` leads to extremly suboptimal
behaviour in use cases where multiple small reads are performed
sequentially, see #69588.
Removal of this option does not break the behaviour of any existing
applications, only increases current consumption in idle by ~10uA until
device runtime PM is enabled.
Signed-off-by: Jordan Yates <jordan@embeint.com>
Can be used only once the SiM3U SoC support has been added.
Developed-by: Michael Zimmermann
Signed-off-by: Reto Schneider <reto.schneider@husqvarnagroup.com>
Some flash/memc drivers like flexspi will want to default the
value of the log level to off to avoid RWW hazard while XIP,
to do this, the logging template must be sourced after the driver
kconfig files so that the default value from the driver is able
to be checked, since logging template introduces an unconditional
default otherwise.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Use the define to send the reset cmd at quad-flash init :
SPI_NOR_CMD_RESET_EN followed by SPI_NOR_CMD_RESET_MEM
when the st,stm32-qspi-nor has the <reset-cmd> property set.
Reports the jedecID correctly.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add missing braces to comply with MISRA C:2012 Rule 15.6 and
also following Zephyr's style guideline.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Remove dead code. The write opcode instruction
is set based on dev_data a couple of lines after.
This was supposed to be in the merged "memory map
support for other modes" PR.
Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
When application code runs from M4 (resides on lower 896KiB of
the internal flash of bank2) and it does write to a block in
the upper 128KiB, write fails sometime (for example failed
1 out of 10 block write based on the tests) due to STRBERR.
As per technical reference manual section 4.7.4 of
STM32H745/755 SoC, application may ignore this error and
continue with write. So check for the flag and return okay
status for write(). Based on our tests, the application write
succeeds even when this error happens and match with document
description. So igoring this error flag is okay during write.
Signed-off-by: Murali Karicheri <murali.karicheri@sandc.com>
Add more clarity to memory map log output.
Use LOG_DBG instead of LOG_INF to signal about
memory map mode being enabled.
Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
REG_X_BASEADDR will be removed from all hal files.
This forces the use of the peripheral base address
Define MSPI_PORT macro for chip drivers
Signed-off-by: Richard Wheatley <richard.wheatley@ambiq.com>
RRAMC peripheral is a secure-only peripheral, and the application
cannot use it directly. While building an application with TF-M
enabled and SOC_FLASH_NRF_RRAM the NRFX_RRAMC selection must
be forbidden.
Signed-off-by: Arkadiusz Balys <arkadiusz.balys@nordicsemi.no>
This variable is only used under DUAL_BANK condition and a warning
is generated in !DUAL_BANK case, so move its definition accordingly.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
When QSPI configuration is the dual-flash, the total
flash size and erase size are doubled. This is handled
with a STM32_QSPI_DOUBLE_FLASH factor which doubles
the values of one qspi component.
Note that SFDP table is for ONE flash component.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The offset is wrong when the second bank is used by M4 as the
offset is relative to the base which is 0. So add the least
significant 6 nibbles from the CONFIG_FLASH_BASE_ADDRESS to
find the sector.
Signed-off-by: Murali Karicheri <murali.karicheri@sandc.com>
Currently flash controller driver builds and runs only on M7.
This patch supports enablement of the driver on M4 CPUs. The
main issue in using the driver on M4 is that LL_GetFlashSize()
to read the flash size works only on M7 as the internal register
is not accessible from M4. So to use the driver on M4, add a dt
property, bank2-flash-size, to configure flash size of bank2.
this will allow gradual support of flash controller driver
on M4 of all supported STMH7 boards by defining the above
dt property and testing it. Currently this is verified only
on STM32H747i-disco board.
Signed-off-by: Murali Karicheri <murali.karicheri@sandc.com>
When using SPI-NOR SFDP autodeteection, the flash size printed to
the log is rounded to 1 MiByte. If flash is smaller than 1 MiByte
it is printed as 0 MiByte.
With this patch smaller flash sizes are printed in kiByte, for instance
512 kiByte is printed correctly.
Signed-off-by: Stefan Petersen <spe@ciellt.se>
Device drivers should not be calling `pm_device_runtime_enable` on
themselves, it should be left up to the application. If automatic
enablement is desired, `zephyr,pm-device-runtime-auto` exists as a
devicetree property.
Signed-off-by: Jordan Yates <jordan@embeint.com>
The `pm_device_runtime_get` and `pm_device_runtime_put` functions work
correctly regardless of whether `PM_DEVICE_RUNTIME` is enabled or not.
Signed-off-by: Jordan Yates <jordan@embeint.com>
The `count` semaphore was being used as an atomic counter, so replace
it with an atomic variable, which is a simpler solution and enables
removing the conditionals with `PM_DEVICE_RUNTIME`.
Signed-off-by: Jordan Yates <jordan@embeint.com>
PR #63973 namespaced generated headers with zephyr/, including generated
syscall headers.
Since then, some new generated syscall header includes have been added
without the zephyr/ prefix, breaking builds when
CONFIG_LEGACY_GENERATED_INCLUDE_PATH is disabled.
This commit adds the zephyr/ prefix to includes for generated syscall
headers where it has been missed.
Signed-off-by: Ben Marsh <ben.marsh@helvar.com>
Add check for returned value from the call to spi_nor_cmd_write
in spi_nor_write.
Fixes#74775
Signed-off-by: Dominik Ermel <dominik.ermel@nordicsemi.no>
Adding the support of the memoryMapped mode
to the flash_stm32_xspi driver through the CONFIG_STM32_MEMMAP
That will allow XiP from the external octo_flash
Erase and Write operation must Abort operations.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Erasing rram is very similar to partial erase on flash.
So we should use the same multiplier as there, 1.5.
0.1 multipler is way to low and was causing timeouts.
Signed-off-by: Martin Tverdal <martin.tverdal@nordicsemi.no>
The ATXP032 is a NOR flash device that supports up to ~100MHz
octal SDR/DDR with 4MB nonvolatile memory.
The device driver uses MSPI bus API and could be used across different
SoC controllers that implement the MSPI bus API.
Signed-off-by: Swift Tian <swift.tian@ambiq.com>
Add support to select the nCS line for XSPI from the device tree.
Disable the nCS override.
This setting only works with series that have an XSPIM (so not H5)
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add the support of the stm32h7rs serie to the flash stm32h7 driver
Remap Flash registers to the stm32h7rs serie.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The stm32 flash driver returns success even though
writing failed when instruction cache was enabled.
Fix by not overriding error code when re-enabling
instruction cache.
Signed-off-by: Riku Karjalainen <riku.karjalainen@vaisala.com>
Refactor the `QSPI_CommandTypeDef cmd_write_en` definition to
a `static const` local variable to eliminate redundant definitions.
This change enhances performance by reducing runtime overhead associated
with initializing `cmd_write_en` in multiple functions.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Add the commands to read and write to/from the xSPI with gpDMA
On the stm32h5 device, the one request for xspi instance
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Configure the xspi clocks domain by the clock domain
as defined by the DTS
Up to 3 possible clock confg : xspix, xspi_ker, xspi_mgr
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Fix compilation error when reset-gpios is enabled.
Undefined reference to dev_cfg variable.
Reset gpio duration needs to be defined, but is not in binding file.
Signed-off-by: Joakim Andersson <joerchan@gmail.com>
Move STM32_MEMMAP outside of SOC_FLASH_STM32.
That allows memory-mapped application to
be built without internal flash controller.
Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
Configure the quad-spi in DualFlash Mode when enabling the MemoryMapped
then reading is possible with memcopy.
DUAL flash mode is possible on stm32 series with QUADSPI_CR_DFM
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Incorrectly placed preprocessor conditions caused exit_dpd
when there has been no instance of a device with
dpd_wakeup_sequence parameter.
Signed-off-by: Dominik Ermel <dominik.ermel@nordicsemi.no>
Signed-off-by: Jan Tore Guggedal <jantore.guggedal@nordicsemi.no>
The commit selects HAS_NO_EXPLICIT_ERASE for Apollo4,
with MRAM, and HAS_EXPLICIT_ERASE for Apollo3 which has Flash,
for a driver that shares code between SoCs.
In case of Apollo4 the no_explicit_erase capability is set to
true, while it remains false for Apollo3.
Signed-off-by: Dominik Ermel <dominik.ermel@nordicsemi.no>
Add explicit_erase capability and set proper value to it,
depending on type of a device.
Select FLASH_HAS_EXPLICIT_ERASE by devices that have program-erase
characteristics and FLASH_HAS_NO_EXPLICIT_ERASE, where needed.
Signed-off-by: Dominik Ermel <dominik.ermel@nordicsemi.no>
The commit adds support for testing non-explicite-erase
device on Flash Simulator. This is addition to already supported
explicit erase before write, aka Flash, type of device behaviour.
Signed-off-by: Dominik Ermel <dominik.ermel@nordicsemi.no>
The commit adds two new API calls:
- flash_fill - that allows to fill selected part of device with
specified value;
- flash_flatten - that allows to erase or fill device with
erase_value, depending on whether driver for the device provides
erase callback.
Signed-off-by: Dominik Ermel <dominik.ermel@nordicsemi.no>
The commit adds and no_explicit_erase capability to flash_parameters,
that indicates whether device is program-erase type device; such
devices, like Flash type devices, require erase prior to writing
random data at any previously programmed location.
This capability should only be set by drivers.
The flash_params_get_erase_cap() function has been added, for parsing
flash_parameters object to obtain erase capabilities of device.
The function returns capabilities as combination of bits representing
them. Currently it will return:
0 -- no erase capabilities
FLASH_ERASE_C_EXPLICIT -- erase required before write of random data.
Additional capabilities have been reserved but are not yet used.
There are following Kconfig options added:
FLASH_HAS_EXPLICIT_ERASE
FLASH_HAS_NO_EXPLICIT_ERASE
that should be selected by device driver to indicate whether
devices served by driver needs erase prior to write.
The above Kconfigs are used to figure out whether app is built
for hardware that requires erase prior to write.
They can be also used to detect that it is attempted to build
some subsystem that will not work with provided hardware, for example
file system that has not been prepared to work with devices that
do not require erase.
Signed-off-by: Dominik Ermel <dominik.ermel@nordicsemi.no>
This change is aborting the memoryMapped mode of the octo-flash
before erasing or writing the NOR. Operations are performed in
command mode.
Reading is always performed in MemoryMapped mode (memcopy)
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Enable the MemoryMapped Mode for the stm32 octoFlash driver
Configure the Flash in MemoryMapped to use in XiP mode.
With this mode the erase and write are not supported.
Address and size are given by the DTS register property.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Namespaced the generated headers with `zephyr` to prevent
potential conflict with other headers.
Introduce a temporary Kconfig `LEGACY_GENERATED_INCLUDE_PATH`
that is enabled by default. This allows the developers to
continue the use of the old include paths for the time being
until it is deprecated and eventually removed. The Kconfig will
generate a build-time warning message, similar to the
`CONFIG_TIMER_RANDOM_GENERATOR`.
Updated the includes path of in-tree sources accordingly.
Most of the changes here are scripted, check the PR for more
info.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Check the return values of commands such as spi_nor_cmd_* and
spi_nor_wait_until_ready and ensure they are propagated back to the
caller on error.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
The commit removes unneeded check for enter_4byte_addr_exist in
the function, as the utility function is supposed to set the address
by parsing enter_4byte_addr parameter, while the enter_4byte_addr_exist
used to exist only for DTS entries that directly set enter-4byte-addr
parameters for a flash node.
The change also moves LOG_DBG reporting enter_4byte_addr before
it is processed, to allow logging what actually function will be working
with, before it does so.
The enter_4byte_addr_exist is removed as it is no longer used anywhere.
Setting of data->flag_access_32bit has been moved in the same code block
as call to the spi_nor_cmd_write, as it can be only consequence of
successful call to that function.
Signed-off-by: Dominik Ermel <dominik.ermel@nordicsemi.no>
This block of code was in the original commit that added
CONFIG_SPI_NOR_IDLE_IN_DPD but later modifications
added acquire_device() and release_device() calls
earlier in spi_nor_configure() and the release_device()
function will have already done the enter_dpd().
Signed-off-by: Mike J. Chen <mjchen@google.com>
In simulated targets the RRAM is not allocated
starting at address 0x0, but on an area allocated
at runtime.
Let's support this, to enable running the
real RRAM driver for simulated targets.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Implement more robust handling for legacy SFDP tables, which may not
implement some of the JEDEC defined DWORDS for SFDP data. Instead of
failing to probe/initialize the flash when these DWORDS are not defined
in the basic flash parameter table, revert to sane defaults for SPI
flash.
Fixes#72051
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This puts the QSPI peripheral into memory-mapped mode when
CONFIG_STM32_MEMMAP is set. Writes and erase put it back into indirect
write mode.
Signed-off-by: Armin Brauns <armin.brauns@embedded-solutions.at>
This CONFIG_STM32_MEMMAP is for enabling the MemoryMapped mode
on external octo or quad spi memory.
In this case, the flash_stm32_read is done in mem map mode
the flash_stm32_erase is not available.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Some stm32 devices with quadspi (like stm32l47x or stm32l48x)
does not support Dual-Flash Mode. Avoid building error even if
the &quadspi node has a <flash-id> property defined.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Introduce a XSPI driver to cover the common XSPI peripherals
of the stm32 mcu: X is for single or quad or octo or hexa
SPI bus access to external memories
DMA not supported in this version
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Select that the STM32 driver has extended operations feature when
the FLASH_STM32_BLOCK_REGISTERS is set.
It allows using only block registers extended operation.
Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
FLEXSPI nor driver uses several LUTs for "scratch" commands during the
SFDP probe phase that are not needed once the flash is configured. Set a
second "end" marker we can use to configure the FLEXSPI MEMC driver, so
that we can indicate the true number of LUTs needed by this driver when
init is completed.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The clk, dqs and ncs pins can be remapped between OSPI instances, but the
driver doesn't support it, yet. Therefore replace hard coded numbers to
device tree optional properties.
Signed-off-by: Samuel Kleiser <s.kleiser@vega.com>
This commit adapts the Ambiq flash controller to support the Apollo3
SOC (e.g. Apollo3 Blue, Apollo3 Blue Plus).
Also uses the Zephyr common IRQ API to replace the Ambiq HAL ones.
Signed-off-by: Aaron Ye <aye@ambiq.com>
The esp_flash*() functions don't return
negative errno codes, so it's return value
should not be used for the flash api functions.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Non-secure images cannot reference NRF_RRAMC_NS because NRF_RRAMC_NS
does not exist.
TF-M will configure RRAMC according to these Kconfig's before booting
the non-secure image so we ifdef out this code.
Also, rewrite the implementation of commit_changes to also work when
the commit task is not available.
Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
Fix incorrect note that write only allows to change value of
bit to zero, where proper information is that change is only allowed
from erase-value to the opposite.
Signed-off-by: Dominik Ermel <dominik.ermel@nordicsemi.no>
The commit adds missing binary or in write operation.
Assuming that program-erase devices only allow switching bits
from erase-value to opposite, in case of 0x00 erase value device
only ones can be written.
Signed-off-by: Dominik Ermel <dominik.ermel@nordicsemi.no>
This commit removes unnecessary usage of the `ARG_UNUSED` macro and
unnecessary initialization of the `ret` variable where its value is
guaranteed to be overwritten by subsequent operations.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Use the most adapted instruction for the sector erase command
It can be 0x20 or ox21 or 0x21DE in octo - DTR mode.
The value is given by the SFDP table and filled in the erase_types
table the during the SFDP discovery process.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The commit adds dependency on Kconfig FLASH_PAGE_LAYOUT to subsystems
that really require it:
FCB, NVS, LittleFS
and removes direct selection from '*.conf' files where no longer
needed.
Signed-off-by: Dominik Ermel <dominik.ermel@nordicsemi.no>
It is impossible to perform flash reads during a flash write. When the
data to write to flash lies in the flash itself, it is buffered in ram
before writing.
Signed-off-by: Lukas Gehreke <lk.gehreke@gmail.com>
Use `pm_device_driver_init` to ensure that init is run correctly
regardless of the power state.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
There has been missing line initializing the hold pin,
which caused SPI NOR device init to fail with -ENODEV,
if property defining such pin has been present in device
definition.
Fixes#70661
Signed-off-by: Dominik Ermel <dominik.ermel@nordicsemi.no>
Modify the SPI Nor driver to be able to have multiple instances at
the same time.
This patch is heavily inspired by the at45 driver.
It was tested on the nRF5340 DK by using the external spi memory two times.
Macros were improved by de-nordic
Signed-off-by: Mehdi Zemzem <mehdi.zemzem2@gmail.com>
The nrfx_qspi driver in nrfx 3.4.0 started checking conditions that
could trigger anomaly 159 on nRF5340 so make sure that QSPI transfers
are only performed with properly configured clocks (PCLK192M undivided
and HCLK128M divided by 2).
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add new devicetree bindings for F4 and L1 series for configuration of
block size used in flash write operations.
Allow byte-size write operations in `flash_stm32f1x.c`. This file is
being shared between F0, F1, F3, L0 and L1 series. L0 and L1 series
allows for single byte writes.
Signed-off-by: Gustavo Silva <gustavograzs@gmail.com>
Add Nuvoton numaker series flash memory controller(RMC) with erase,
read & write features of soc-flash.
Signed-off-by: cyliang tw <cyliang@nuvoton.com>
HAL_OSPI_AutoPolling is checking is the status match
happened in a busy loop. That CPU intensive operation
can cause starvation of other tasks especially on flash
erase operations which can take seconds to complete.
So, replace the use of HAL_OSPI_AutoPolling with
HAL_OSPI_AutoPolling_IT. The match results
HAL_OSPI_StatusMatchCallback being called.
Signed-off-by: Miika Karanki <miika.karanki@vaisala.com>
Opcodes for erase is taken from jedec basic flash parameter table
These expects 3 byte addresses.
When running with 4 byte addresses, opcodes to be used shall be taken
from JEDEC 4-byte Address Instruction Parameter table
Signed-off-by: Brian Juel Folkmann <bju@trackunit.com>
Adds conditional usage of locking mechanisms to allow building
without multithreading.
Signed-off-by: Mateusz Michalek <mateusz.michalek@nordicsemi.no>
Now RRAMC is set to use up to 512 B burst writes by default as most
time effective.
Requested slot time was changed to 8000 us for that case, as this is
required in order to hold the longest write operation.
Drivers differs slot duration depending on configured RRAMC buffers count
(CONFIG_NRF_RRAM_WRITE_BUFFER_SIZE).
Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
When radio-synchronization was on
(CONFIG_SOC_FLASH_NRF_RADIO_SYNC_NONE=n) context of writing was shifted
by 4 instead of write-length (this caused redundant, self-shortening
writes to the same block.)
write-len was unset when requested write len was less than
RRAM_MAX_WRITE_BUFFER.
Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
Signed-off-by: Jakub Zymelka <jakub.zymelka@nordicsemi.no>
Added synchronization with BLE radio operation to the RRAM flash
driver. The implementation is using framework which is already
provided for nrf52's flash driver.
Additional added resource locking mechanism while driver does writing
which solves mutual exclusion write access problem.
Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
Signed-off-by: Jakub Zymelka <jakub.zymelka@nordicsemi.no>
Added a simple driver for RRAM. It is implemented as a flash driver,
because the "RRAM eFlash" macro obeys flash-like constraints.
Although users are not required to erase before write.
Signed-off-by: Jakub Zymelka <jakub.zymelka@nordicsemi.no>
Address and size are given by the DTS register property
of the qspi nor : to be used by the qspi driver.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Address and size are given by the DTS register property
of the ospi nor : to be used by the ospi driver.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Support SFDP probe in flexspi nor driver. This probe will allow the
flash driver to dynamically configure quad spi flashes for 1-4-4 mode,
expanding the flash chips supported with this driver.
The following data is read from the SFDP header:
- quad enable method
- fast read command (1-4-4 is maximum supported)
Fixes#55379
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add support for reclocking the FlexSPI on NXP iMX RT10XX. This
functionality requires an SOC specific clock function to set
the clock rate, since the FlexSPI must be reset directly
before applying the new clock frequency.
Note that all clock constants are defined in this commit, since the
memc flexspi driver now depends on a clock node being present.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
For the flash driver, the base address is the MCU internal flash
address (usually 0x8000000). This PR gets the that address
from the device tree node "st,stm32-nv-flash"
instead of relying on the CONFIG_FLASH_BASE_ADDRESS
which might differ when building for another flash memory.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This file uses several functions which are extensions to the the
std C library. Let's explicity select one of the extensions
which includes it instead of relaying on somebody having
set it for this file somewhere else.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
The implementation uses the same approach as STM32F1x.
Program/erase speed can be set by setting 'write-block-size' flash
property to 1, 2, 4 or 8.
Signed-off-by: Patryk Duda <patrykd@google.com>
Provide different loop delays to `wait_until_ready` based upon the
operation that we are waiting for.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Don't monopolise the CPU in `spi_nor_wait_until_ready`. For slow flash
chips, operations can take minutes (Full chip erase on MX25R is listed
as 120s typical, 240s max).
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
This commit updates the driver to use the flash layout pages,
rewriting it to utilize the flash_page_layout.c driver to
avoid duplicate code.
Signed-off-by: Bjarki Arge Andreasen <bjarkix123@gmail.com>
Adjusted the code to guarantee resource release irrespective of operation
success or failure.
Fixes#67336
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
This is a follow-up to commit ea1be7f242.
After the driver performs its initialization, it needs to deactivate
the QSPI peripheral. Otherwise, the peripheral would unnecessarily
consume power until some QSPI operation is performed (and only then
it will get deactivated), what depending on the application may take
a significant amount of time.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Added Kconfig assignment of qspi timeout.
Per nrfx v3.2 addition of qspi timeout in config
struct.
Signed-off-by: Kelly Helmut Lord <kellyhlord@gmail.com>
This fix adds the STM32L4P5xx to the list of devices that have an
offset-to-page shift calculation of 12 bits. Previously, the driver
would only shift the offset by 11 bits when calculating the page to
erase.
This would prevent the driver from erasing the correct page.
Signed-off-by: George Beckstein <george.beckstein@ampaworks.com>
Erase operation with block of 64KByte
larger size than the default 4K sector size
if the flash supports.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
When Bluetooth is enabled, it is required to arbitrate flash accesses
between RF and write accesses (for user activity).
A dedicated flash manager is provided as part of STM32WBA BLE lib.
Implement a dedicated driver using FM Apis to handle RF activity.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Boot into the deep power down state when `SPI_NOR_IDLE_IN_DPD` is not
enabled. DPD is the correct hardware state for the `SUSPENDED` software
state. Without this change, it takes a cycle of
`SUSPENDED->ACTIVE->SUSPENDED` to get to the low power state.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
STM32U5X has 128k/256k/512k/1M/2M dual bank Flash.
The address of the 2 bank are continuous, so it's no need a "Dummy page"
in "stm32_flash_layout", which cause wrong slot1 section (for secondary
image), and the BANK2_OFFSET is not right either, which cause
"flash_stm32_valid_range" return a failure.
To fix the issue, just set CONFIG_FLASH_SIZE to STM32_SERIES_MAX_FLASH
Tested on NUCLEO-U545RE with mcuboot.
Signed-off-by: Weifeng Li <weifeng.li@aofrio.com>
So far the driver first changed the configuration of the flash chip
and after that checked the signature of that chip. This could lead
to improper change of the chip configuration if the actually found
one was different than that specified in devicetree.
This commit reverses the order of these two initialization steps and
also restructures a bit the initialization code.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
