Add support for LAN8650/1 Rev.B1. As per the latest configuration note
AN1760 released (Revision F (DS60001760G - June 2024)) for Rev.B0 is also
applicable for Rev.B1. Refer hardware revisions list in the latest AN1760
Revision F (DS60001760G - June 2024).
https://www.microchip.com/en-us/application-notes/an1760
Signed-off-by: Parthiban Veerasooran <parthiban.veerasooran@microchip.com>
10BASE-T1S PHYs can operate in either CSMA/CD or PLCA mode. PLCA mode
needs some set of parameters like node id, node count, max burst count,
burst timer and TO (Transmit Oppertunity) timer to be configured. OPEN
Alliance TC14 specification defined a set of PLCA registers to configure
PLCA mode. The below APIs are implemented for PLCA mode.
genphy_set_plca_cfg() - to configure PLCA settings.
genphy_get_plca_cfg() - to get the configured PLCA settings.
genphy_get_plca_sts() - to get the PLCA status like active or inactive.
These APIs are implemented as generic library so that all 10BASE-T1S
PHYs can use these APIs to configure/access PLCA settings to avoid
duplication of code.
Signed-off-by: Parthiban Veerasooran <parthiban.veerasooran@microchip.com>
On the interrupt handling, one thread per driver instance is involved
into monitoring the semaphor, sends inside the gpio callback triggered
by the gpio interrupt. Each time, when the link parameters are change,
the DM8806 is generating the gpio interrupt. After getting semaphor,
the application callback function which was linked during initialization
process is called to get the new link parameters with standard API
calls
Signed-off-by: Robert Slawinski <robert.slawinski1@gmail.com>
New driver for Davicom DM8806 PHY. Driver is using standar mdio API
to manage the DM8806 switch controller. Register access needs the
PHY addres or switch address to be one of five possible values, since
DM8806 has built-in five PHY's. These values should be defined in the
application .dts file. One DM8806 ethernet port must corresponds with
one ethernet PHY node with two properties for ethernet port: one for
PHY address and one for switch address - <reg> for register access from
Internal PHY Register area and <reg-switch> for register access from
Switch Per-Port Registers area. Device tree example below:
example device-tree:
dm8806_phy: ethernet-phy@0 {
reg = <2>;
reg-switch = <8>;
compatible = "davicom,dm8806-phy";
status = "okay";
davicom,interface-type = "rmii";
reset-gpio = <&gpiod 2 GPIO_ACTIVE_LOW>;
interrupt-gpio = <&gpioc 1 GPIO_ACTIVE_HIGH>;
};
Signed-off-by: Robert Slawinski <robert.slawinski1@gmail.com>
Add driver for Realtek RTL8211F 10/100/1000M ethernet PHY.
This driver implements vendor specific behaviour like
detecting link state change by GPIO interrupt, which is not
present in the generic MII driver.
Fixes: #66348
Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com>
Add support for similar adin1100 phy, boath are 10Base-T1L,
only difference is that adin1100 connects through r/mii.
Signed-off-by: Angelo Dureghello <angelo@kernel-space.org>
drivers: eth: phy: tja1103: Handle link change
These changes enable -
TJA1103 driver to gracefully handle Link connect or disconnect events
between Ethernet PHY and its link partner and notify it to the
upper network layers
Signed-off-by: Sumit Batra <sumit.batra@nxp.com>
Add Driver for KSZ8081 Ethernet PHY. The Generic MII Driver
is not sufficient to use for this PHY chip which has special
vendor implemented behaviors.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Adds the tja1103 enet phy for setting phy options on the mr_canhubk3.
Co-authored-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Co-authored-by: Peter van der Perk <peter.vanderperk@nxp.com>
Signed-off-by: Benjamin Perseghetti <bperseghetti@rudislabs.com>
Decouples the generic MII PHY driver from the adin2111 driver by making
it depend on an ethernet-phy compatible devicetree node rather than the
adin2111 driver not being enabled. This makes it possible to add the
adin2111 driver to tests/drivers/build_all/ethernet
Signed-off-by: Maureen Helm <maureen.helm@analog.com>
Adds PHY driver. Works via MDIO API and
exposed ADIN2111 MDIO Clause 45
functions.
Link status detection is triggered by
ADIN2111 driver within offloaded IRQ
handler.
Supports:
- LED0, LED1 enable/disable
- Fatal HW error detection
- AN 2.4V tx mode enable/disable
The initialization order is important.
PHY 2 must be initialized after PHY1.
Therefore, it shall be defined after the 1st one
in the devicetree.
Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
This commit adds support for Ethernet PHY drivers via a PHY API.
It also includes a driver for a generic MII compliant PHY
which supports most PHYs on the market.
Separating PHY driver from the SoC specific Ethernet driver
simplifies the Ethernet driver code and enables code re-use.
Drivers for specific PHYs with more advanced features, such as
RGMII delay in PHY can be developed independent of the Ethernet
MAC driver.
Signed-off-by: Arvin Farahmand <arvinf@ip-logix.com>
