This revert the idea of 3fa7d78 from #78845.
The 3rd level IRQ APIs won't compile when
CONFIG_3RD_LEVEL_INTERRUPT_BITS=0.
Updated testcases accordingly.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
For some target and optimization level combinations (aarch64 and -O2, for
example), GCC will over align _isr_list_sname instances. The local isr
declaration parser doesn't expect the extra padding that may be introduced
and will produce unexpected errors about bad IRQs (`error: IRQ 1903323438
(offset=0) exceeds the maximum of 42`, for example). Prevent this issue by
forcing the expected alignment of _isr_list_sname.
Fixes#81254
Signed-off-by: Jonathon Penix <jpenix@quicinc.com>
This revert the idea of 3fa7d78 from #78845.
The 3rd level IRQ APIs won't compile when
CONFIG_3RD_LEVEL_INTERRUPT_BITS=0.
Updated testcase accordingly.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
Test multilevel-irq APIs with interrupt number generated from
the devicetree to make sure that they work in sync.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
Trying to enable LTO when CODE_DATA_RELOCATION is already enabled
produces a warning.
This commit prevents twister from building such combinations for
arch.shared_interrupt.lto.
Signed-off-by: Reto Schneider <reto.schneider@husqvarnagroup.com>
With picolibc being the default C library, we need to explicitly include
testing against the minimal C library for kernel components.
Signed-off-by: Keith Packard <keithp@keithp.com>
This test fails when icount is disabled, so enable it
See 7bdc621ba9 which disabled icount by
default for this platform.
Signed-off-by: Keith Packard <keithp@keithp.com>
Kernel is being built the same way for all those tests and there is not
much related to the linker generator in any of those tests. Just keep a
small set of tests to have needed coverage in the kernel.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Twister now supports using YAML lists for all fields that were written
as space-separated lists. Used twister_to_list.py script. Some artifacts
on string length are due to how ruamel dumps content.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
This reverts the commit 7d8a119213
because GCC is now configured to not emit ldp/stp Qn instructions for
consecutive 32-byte loads and stores, and the nested interrupt handling
failure due to the missing emulation of these instructions no longer
occurs.
For more details, refer to the GitHub issue #49491 and #49806.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This commit disables the `arch.interrupt` test on the ARM64 QEMU
targets (`qemu_cortex_a53` and `qemu_cortex_a53_smp`) because the
nested interrupt test fails when compiled with GCC 12.
Revert this commit when the GitHub issue #49491, which tracks this bug,
is fixed.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Move the direct interrupt test to tests/arch/x86/direct_isr. Two
reasons:
1. The direct interrupt is only for x86. It's arch-specific.
2. And it need extra gcc option to pass the build, that will
include testsuite number. Although it seems like we add a
extra testsuite for it, actually we can reduce whole tests
configuration in tests/kernel/interrupt. And also make this
test more generic as it used to be.
Signed-off-by: Enjia Mai <enjia.mai@intel.com>
This commit adds an additional test case for several kernel test suites
to ensure that the linker script generator is working correctly for a
subset of the Zephyr test suites.
The ensures that the basic functionality of the linker script generator
is working while still keep the performance impact on CI at a minimal
level.
Using the kernel tests is a trade-off between testing coverage of the
linker script generator and the time it takes to complete CI.
The kernel tests is considered to have the broadest coverage of various
features important for the generated linker script.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
Add test cases of direct interrupt for arch x86 and posix.
We register two direct interrupt at build time, then triggering
interrupt and check if ISR handler has executed or not. We also
check irq_enable and irq_disable works.
Why we add an extra compiler option "-mgeneral-regs-only" to make
it works in arch x86. because there might be some existing x87
instructions executing inside interrupt context.
Signed-off-by: Enjia Mai <enjiax.mai@intel.com>
tests/kernel/interrupt tests interrupt trigger functionality,
however, the Non-Secure Cortex-M mode does not have full control
of the interrupt handling, so this test cannot be guaranteed to
pass when executing in Non-Secure mode. Filter the test out for
Non-Secure Cortex-M builds.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
GICv3 is now support for SGI generation and test case is updated
to use GICv3 apis. bcm958402m2_a72 can be enabled now.
Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com>
The test itself handles correctly whether gen_isr_table
style dynamic interrupts are supported or not, there's
no need for an alternate scenario.
The tests work fine on riscv32 now, remove the exclusion.
Add a github link as to why Nios II is still excluded.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
There are two set of code supporting x86_64: x86_64 using x32 ABI,
and x86 long mode, and this consolidates both into one x86_64
architecture and SoC supporting truly 64-bit mode.
() Removes the x86_64:x32 architecture and SoC, and replaces
them with the existing x86 long mode arch and SoC.
() Replace qemu_x86_64 with qemu_x86_long as qemu_x86_64.
() Updates samples and tests to remove reference to
qemu_x86_long.
() Renames CONFIG_X86_LONGMODE to CONFIG_X86_64.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
* add the case for ARC in yaml after dynamic and direct irq are
supported
* fix the bug that index in sw_isr_table should have a offset of
CONFIG_GEN_IRQ_START_VECTOR
Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
As we have re-worked the test code, and the test-case can run
on Cortex-M platforms on any available and implemented NVIC
IRQ lines, we do not need to exclude these ARM boards anymore.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Platforms which use the GEN_SW_ISR mechanism for interrupt handling
can make use of a really simple whitebox trick for verifying that it
worked (i.e. that the pointer and argument get placed in the table
correctly).
Easy and simple way to get some coverage for dynamic IRQs, which is
currently entirely missing. Long term we'll want to replace this with
a test that uses the API directly and chooses an arch-specific vector
to set, and triggers it using arch-specific code, but that's quite a
bit more effort and for now we need to land patches to
z_irq_connect_dynamic() which show test coverage.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Exclude the two variants of smt32_min_dev (stm32_min_dev_black and
stm32_min_dev_blue) from kernel tests.
Signed-off-by: Siddharth Chandrasekaran <siddharth@embedjournal.com>
The test assumes that the last to IRQ numbers will be free, this isn't a
valid assumption and now that we detect multiple ISRs registering for
the some IRQ line, we see failures because of this assumption on some
platforms. Exclude those platforms from this test for the time being.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This is a new test and we have riscv32 failing on that all of the
sudden. Disabling while we look into it and identify if that is a
testcase issue or not.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This test is intended to verify the interrupt nesting.
Interrupt nesting feature allows an ISR to be preempted
in mid-execution if a higher priority interrupt is signaled.
The lower priority ISR resumes execution once the higher
priority ISR has completed its processing.
Signed-off-by: Ajay Kishore <ajay.kishore@intel.com>
