Following changes in e35ac8f and 14c1b4a to how external Q/OSPI Flash
nodes are declared in DT for boards with STM32 SoCs, FLASH_BASE_ADDRESS
needs to be set manually similar to XSPI Flash, so that it does not
default to (dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) which gives 0.
This change is critical for running apps with MCUboot from external
Q/OSPI Flash.
Signed-off-by: Abderrahmane JARMOUNI <git@jarmouni.me>
There is no need to call stm32_pwr_wkup_pin_cfg_pupd() because
the SoC does not have a pull-up/pull-down on the WKUP pin.
Call LL_PWR_ClearFlag_SB() before entering StandBy power mode.
Signed-off-by: Oleh Kravchenko <oleg@kaa.org.ua>
Check for STM32F1 series was done with "#ifdef SOC_SERIES_STM32F1X"
but this symbol comes from Kconfig.
Use the correct "CONFIG_SOC_SERIES_STM32F1X" instead.
Signed-off-by: Oleh Kravchenko <oleg@kaa.org.ua>
Utilize a code spell-checking tool to scan for and correct spelling errors
in `Kconfig` files within the `soc` and `subsys` directory.
Additionally, incorporates a fix recommended by the reviewer.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
This patch allows to link the request of the linklayer for a
temperature calibration to the temperature driver.
The linklayer will then adapt and trigger its calibration related to
the current temperature.
Signed-off-by: Romain Jayles <romain.jayles@st.com>
Add LINKLAYER_PLAT_EnableBackupDomainAccess() and
LINKLAYER_PLAT_DisableBackupDomainAccess() to use Zephyr resources
that use a reference counter for access requests, for enabling
and disabling access the BackupDomain resources.
Bump hal_stm32 module to the revision integrating related stm32wba
BLE updates.
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Use recently added SoCs functions to request access to SoC backup
domain resources These function use a reference counter to track these
request and ensure the resources are accessible as long as at least a
consumer requires access.
Fixes issue 90942.
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Add SoC functions to enable/disable STM32 backup Domain access
and use a reference counter to track requests. These helper functions
may be called from a interrupt context. On domain access enable, the
function loops until written bit is set however this is expected to be
effective after very few clock cycles and seems not even required
(not mentioned in any SoC documentation). The loop is preserved as
used in previous implementation.
Among all supported STM32 SoCs, only STM32C0 and STM32WB0 series do not
implement this mechanism hence add option CONFIG_STM32_BACKUP_PROTECTION
that is enabled for all SoC series but these 2.
Fixes issue 90942.
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Make axisram2 which is used in fsbl mode available as well to
chainloaded application in order not to loose 1M of RAM
In order to avoid conflicts with bootloader, verify that code + ro data
of the loaded application won't go further than bootloader start address.
This is done with a linker assert.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
STM32U0 specific changes to enable the PM feature.
Base on the power-related code from the STM32U5 target.
Signed-off-by: Mickael Bosch <mickael.bosch@linux.com>
Modify the STM32 pinctrl driver and SoC-specific pinctrl macros
to introduce support of the st,stm32n6-pinctrl variant.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
Set the LTDC buffer alignment to 256 in order to avoid an
issue when accessing to PSRAM via XSPI.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
The SMH attribute when using the XSPI PSRAM is set to EXTERNAL (2)
within the driver hence set default for both LTDC and video
buffer SMH attribute to 2 if all conditions are validated.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Add a linker script for the stm32mp2x soc series. It includes the
standard arm cortex-m linker and adds standard zephyr relocation
sections.
Replace the rom_start section name with .isr_vectors in the linker
script. This is necessary for the zephyr firmware to be started by the
remote proc driver which expects the section containing the vector table
to be named .isr_vectors.
Signed-off-by: Youssef Zini <youssef.zini@savoirfairelinux.com>
Add initial soc support for the stm32mp2x series, including
initial Kconfig entries and default configuration files.
This enables Zephyr to recognize and build for the stm32mp2x series,
taking the stm32mp257f_ev1 as a baseline.
Includes:
- Kconfig and defconfig files for SoC selection and defaults
- soc.h for hal headers
- CMakeLists.txt for build system integration
- soc.yml update to register the new SoC
System Clock is configured statically from DTS. So no initialization
hook or soc.c needed.
Signed-off-by: Youssef Zini <youssef.zini@savoirfairelinux.com>
The STM32 signing tool (STM32_SigningTool_CLI) is invoked as a post-build
command to generate a signed Zephyr binary, which is required to run from
flash on N6 series. If the file specified as output already exists, the
tool will by default prompt to confirm it should be overwritten. However,
when invoked from the build system rather than a terminal, this prompt
will break the build (freeze during the "Linking zephyr.elf" step). This
can be seen by building the same application twice in a row, as the second
build will not be different enough to make the build artifacts be deleted
and thus the (old) signed image will be seen by the tool.
Invoke the tool in silent mode such that user is never prompted. This fixes
build failures while still working as intended (if present, the existing
signed image will get overwritten properly).
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
Restore main stack size to the default value since fake entropy
implementation from mbedtls is replaced by STM32 entropy driver.
Signed-off-by: Ali Hozhabri <ali.hozhabri@st.com>
On dual-core STM32H7, the Cortex-M4 core is supposed to wait until the
Cortex-M7 initializes the system before starting to execute. CM7 should
signal this by locking a specific HSEM, which CM4 should poll until locked.
However, the logic on the Cortex-M4 side was reading the "RLR" register of
HSEM, which *locks the semaphore on read* - in turn, this makes the CM4
start directly since it sees that the semaphore is locked (by itself).
Use proper LL API to read HSEM status - which will read the "R" register
instead - to make sure CM4 doesn't begin execution earlier than it should.
Suggested-by: hglassdyb
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
The fifth HSEM (#define is equal to 4 due to zero-indexing) is used on
STM32H7 to synchronize the two cores. Update the comment above the SEMID
define to reflect this alternate usage. Also remove the associated define
CFG_HW_ENTRY_STOP_MODE_MASK_SEMID, which is unused.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
Reorder the HSEM semaphore ID definitions to be sorted by ascending value.
The dummy defines are also changed to be sorted in the same order. The
definitions for STM32MP1 are already in an order that follows this order
so they don't need to be changed.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
Adds skeleton dtsi for u5f9 for u5g9 to inherit from
Moves the peripheral nodes into dtsi's that actually has the peripheral
and includes them for SoC's higher in the series where applicable.
signed-off-by: Harris Tomy <harristomy@gmail.com>
Several drivers checked for the presense and availability of data cache
through Kconfig symbol. This is supported according to the current
documentation, but the symbol DCACHE masks two types of cache devices: arch
and external caches. The latter is present on some Cortex-M33 chips, like
the STM32U5xx. The external dcache is bypassed when accessing internal
SRAM and only used for external memories.
In commit a2dd232410 ("drivers: adc: stm32: dma support") the rationale
for gating dcache for adc_stm32 behind STM32H7X is only hinted at, but
reason seems to be that it was the only SOC the change was tested on. The
SOC configures DCACHE=y so it is most likely safe to swap the SOC gate for
DCACHE.
The DCACHE ifdefs are now hidden inside the shared stm32_buf_in_nocache()
implementation.
Signed-off-by: Henrik Lindblom <henrik.lindblom@vaisala.com>
This commit is retrieving the config FLASH_BASE_ADDRESS
from the XSPI node of the stm32 device dtsi <reg> property of the
"st,stm32-xspi" node. For example the CONFIG_FLASH_BASE_ADDRESS
is 0x90000000 and application is linked for that address.
Size is given by the size property of the "st,stm32-xspi-nor" node.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add config and overlay to samples for testing stop/standby modes:
- samples/boards/st/power_mgmt/blinky
- samples/boards/st/power_mgmt/wkup_pins
I've measured consumption for each low-power mode:
- stop (regulator in run mode) ~217 uA
- stop (regulator in low-power mode) ~206 uA
- standby mode ~3.5 uA
Low-power mode wakeup timings from the datasheet,
but it barely meets these in reality:
- stop (regulator in run mode) 3.6 us
- stop (regulator in low-power mode) 5.4 us
- standby 50 us
It's possible to use RTC as idle timer to exit from stop mode.
Signed-off-by: Oleh Kravchenko <oleg@kaa.org.ua>
Use the Zephyr cache API in soc initialization code instead of calling the
HAL directly. The change does not modify the pre-existing cache settings,
just changes the path they are enabled.
Signed-off-by: Henrik Lindblom <henrik.lindblom@vaisala.com>
Remove the sanity check between Cube HAL SMPS symbol and Kconfig SMPS
configuration.
SMPS is available on all STM32H7R/S SoC, so misalignment isn't possible.
Additionally, point to the hal commit which revert the fix which was done
on hal_stm32 to add this symbol.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Introduces config file entries for STM32F401XD variants. The
STM32F401XD family is related to the STM32F401XE family but with a
reduced flash memory.
Signed-off-by: Ricardo Rivera-Matos <ricardo.rivera-matos@cirrus.com>
The samples/subsys/llext/shell_loader test fails when running as a
twister test on the stm32mp135f_dk/stm32mp135fxx platform, with the
following error:
soc/st/stm32/stm32mp13x/soc.c:46:36:
error: array type has incomplete element type 'struct arm_mmu_region'
46 | static const struct arm_mmu_region mmu_regions[] = {
This commit adds the missing arm_mmu.h include to fix the build issue.
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
This renames the STM32_PWR_WKUP_PIN_SRC_x symbols to better match
their meaning. It also adds a new symbol (STM32_PWR_WKUP_PIN_NOT_MUXED)
for SoCs without wake-up mux support.
Signed-off-by: Tomáš Juřena <jurenatomas@gmail.com>
STM32F439 SoC is an STM32F429 with an integrated crypto/hash processor
providing hardware acceleration for encryption (AES and TDES) and hash
(MD5, SHA-1 and SHA-2).
Signed-off-by: Mathieu Anquetin <mathieu.anquetin@groupe-cahors.com>
