Commit Graph

9 Commits

Author SHA1 Message Date
Jonathan Nilsen
b18c326946 soc: nordic: move nrf_ironside from drivers/firmware to soc/nordic
Move the IronSide APIs to soc/nordic from drivers/firmware since
these are vendor specific APIs. The header files are now included
from <nrf_ironside/*.h>. Adjust code that uses these APIs accordingly.

Also move the DT binding for "nordic,ironside-call" from
bindings/firmware to bindings/misc.

Signed-off-by: Jonathan Nilsen <jonathan.nilsen@nordicsemi.no>
2025-07-02 17:57:45 -05:00
Grzegorz Swiderski
75dd614437 drivers: firmware: nrf_ironside: Update the spelling
s/IRONside/IronSide/g

Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
2025-07-02 17:57:45 -05:00
Dave Joseph
95c20c338c drivers: firmware: TISCI driver support
Added TISCI driver for supported devices using the binding ti,k2g-sci.
This is used to communicate via the secury proxy channel for clock,
resource and power domain management.
Refer: https://software-dl.ti.com/tisci/esd/latest/2_tisci_msgs/general/TISCI_header.html

Signed-off-by: Dave Joseph <d-joseph@ti.com>
2025-06-23 15:54:34 +01:00
Grzegorz Swiderski
47df9ec981 drivers: firmware: Add support for IRONside calls
IRONside calls are remote procedure calls which comprise the runtime
interface of Nordic IRONside SE. They are realized using a simple IPC
mechanism.

A local domain (client) issues requests to the server by exchanging data
in shared memory, which is divided into evenly sized buffers. The client
selects a buffer, writes a request into it, and sends it to the server.
The server processes that request and writes a response into the same
buffer before returning it to the client.

This patch adds the initial client-side implementation on top of MBOX.
It features cache management and a blocking alloc/dispatch/release API
for synchronous, zero-copy transfers.

A new devicetree binding is added to support this implementation. It is
patterned after the `zephyr,ipc-*` bindings, where each node associates
a pair of mailboxes and a shared memory region.

Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
2025-04-29 17:54:41 +02:00
Qiang Zhao
c412ee4597 drivers: firmware: scmi: add cpu domain protocol
Added helpers for NXP SCMI cpu dmomain protocol.

Signed-off-by: Qiang Zhao <qiang.zhao@nxp.com>
2025-04-21 22:03:27 +02:00
Yangbo Lu
7c57fec0d0 drivers: firmware: scmi: add power domain protocol
Added helpers for ARM SCMI power dmomain protocol.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2025-01-15 19:03:00 +01:00
Laurentiu Mihalcea
6b689d0207 firmware: scmi: add support for pinctrl protocol
This includes helper function for pin configuration
and a DT binding for the pinctrl DT node.

There's two important notes to be made regarding this
protocol:

* pinctrl drivers have no subsytem API to implement as opposed
to clock control drivers. Because of this (and the fact that
`pinctrl_configure_pins()` doesn't require a `struct device`
handle) the pinctrl driver consists only of a helper function,
which implements the `PINCTRL_CONFIGURE_PINS` command.
Additionally, the `scmi_protocol` structure is defined inside
the pinctrl helpers source file to avoid redundant code
(otherwise, each SCMI-based pinctrl driver would have to define
it its source file).

* each vendor may have their own set of pin propeties and DT
representations for them. Because of this, there can't be a
generic, SCMI-based pinctrl driver. As such, each vendor who
wants to use the SCMI support for pinctrl operations will have
to implement their pinctrl driver (which, to put it simply,
revolves around implemeting `pinctrl_configure_pins()`) and
make use of the pin configuration function introduced in this
commit. Moreover, this means that each vendor will have control
over the way their pin properties are encoded in the
`scmi_pinctrl_settings` structure.

Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
2024-08-19 10:05:16 -04:00
Laurentiu Mihalcea
350e36a47a firmware: scmi: add support for clock management protocol
This includes:
	1) Source containing helper functions, each
	implementing a command from the clock management
	protocol.

	2) A clock controller driver making use of said
	helper functions and implementing the clock
	subsystem API.

	3) A DT binding for clock protocol node.

Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
2024-08-19 10:05:16 -04:00
Laurentiu Mihalcea
413c77cf4e firmware: introduce SCMI core support
Introduce core support for ARM's SCMI (System Control and
Management Interface). This includes:

* shared memory (SHMEM) driver. This consists of a suite
of functions used to interact with the shared memory area.

* shared memory and doorbell-based transport layer driver.
Data is passed between platform and agent via shared
memory. Signaling is done using polling (PRE_KERNEL) and
doorbells (POST_KERNEL). This makes use of Zephyr MBOX API
(for signaling purposes) and the SHMEM driver (for polling
and data transfer).

* core driver - acts as glue between transport and protocol
layers. Provides synchronized access to transport layer
channels and channel assignment/initialization.

* infrastructure for creating SCMI protocols

This is based on ARM's SCMI Platform Design Document: DEN0056E.

Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
2024-08-19 10:05:16 -04:00