The Quectel BG95 binding currently marks mdm-power-gpios as
required. This fits designs that expose the PWRKEY pin, but the
BG95-M3 in Mini PCIe form-factor boots automatically via its
on-module “Automatic Power-On Circuit” and does not route
PWRKEY to the card edge.
Signed-off-by: Van Petrosyan <van.petrosyan@sensirion.com>
SENT, PSI5, Virtio where all recently added types. Add them to the
binding-types.txt file so that their full name can be displayed in the
documentation.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Description of parameters in st,control property didn't match the values
used in the code.
Modify the description to match with the current driver implementation.
Also add a description for reg property to help setting it properly and
add corresponding dt-bindings.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Move the IronSide APIs to soc/nordic from drivers/firmware since
these are vendor specific APIs. The header files are now included
from <nrf_ironside/*.h>. Adjust code that uses these APIs accordingly.
Also move the DT binding for "nordic,ironside-call" from
bindings/firmware to bindings/misc.
Signed-off-by: Jonathan Nilsen <jonathan.nilsen@nordicsemi.no>
This commit adds a device-tree prop for the audio streaming
terminals to specify the bInterval values for the Isochronous
endpoints.
Signed-off-by: Victor Brzeski <vbrzeski@gmail.com>
AXISRAM3/4/5/6 nodes are added as children of their respective controller.
They're declared as "zephyr,memory-region" and disabled by default.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Fixed typo whereby the description field started with `description: |`
instead of actual description.
Also added a proper title field while at it
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Add driver for Microchip PolarFire SoC (MPFS) peripheral clock and soft
reset control.
Normally, the peripheral clocks and reset state are controlled by the
Hart Software Services (HSS) running on the Monitor processor. As an
alternative to using HSS services, applications can now enable the reset
controller in a device tree overly, for example:
&reset {
status = "okay";
};
&uart4 {
resets = <&reset MSS_RESET_ID_MMUART4>;
};
Embedded the reset controller node in system controller node.
Signed-off-by: Frank Kühndel <frank.kuehndel@embedded-brains.de>
Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>
Signed-off-by: Conor Paxton <conor.paxton@microchip.com>
Introduce a new USB Video Class (UVC) implementation from scratch.
It exposes a native Zephyr Video driver interface, allowing to call the
video_enqueue()/video_dequeue() interface. It will query the attached
video device to learn about the video capabilities, and use this to
configure the USB descriptors. At runtime, this UVC implementation will
send this device all the control requests, which it will send to the
attached video device. The application can poll the format currently
selected by the host, but will not be alerted when the host configures
a new format, as there is no video.h API for it yet.
Signed-off-by: Josuah Demangeon <me@josuah.net>
TI MSPM0 SoC series has General Purpose Timer and Advanced control timers
with Compare block which is used to generate time expiry and output
waveform like PWM. Add driver support for MSPM0 PWM output.
Signed-off-by: Saravanan Sekar <saravanan@linumiz.com>
Two DMA channels are assigned to TX and RX respectively:
- A TX DMA single request is asserted when there is space in the FIFO.
- A RX DMA single request is asserted when data is in the FIFO.
Signed-off-by: Julien Panis <jpanis@baylibre.com>
Strictly speaking not a problem for in-tree tooling, but better to
have all binding files follow the same naming convention.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Update the RaspberryPi CSI camera connector nexus gpio in order to only
expose the list of GPIO pins in order to support both 15-pin and 22-pin
connectors as well as 15-pin to 22-pin conversion cables.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Support added for power domain regulation using TISCI added for
devices using the binding ti,sci-pm-domain.
This driver relies on the TISCI layer to make calls to the
device manager core to perform power management.
Signed-off-by: Dave Joseph <d-joseph@ti.com>
Change license owner to Prevas due to initially wrong owner due to company
mix-up during co-development.
Signed-off-by: Jeppe Odgaard <jeppe.odgaard@prevas.dk>
Add configurations for setting the pad drive strength and the
interrupt active high/low and od/pp.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
I2S driver support standard format, short/long sync, left/right justified.
Supporting 2 channels as a default.
Signed-off-by: Lewis Lee <llee@ambiq.com>
The CH32V003 has a 8 channel, 10 bit onboard ADC. Add an immediate
mode driver and the appropriate pinctrl bindings. Note that the
CH32V003 GPIO pins have both a floating input and an analogue input
mode, and the pinctrl is needed to put the pin in analogue mode.
Signed-off-by: Michael Hope <michaelh@juju.nz>
The WCH External Trigger and Interrupt controller (EXTI) supports
between 8 and 22 lines where each line can trigger an interrupt on
rising edge, falling edge, or both edges. Lines are assigned to a
group, and each group has a separate interrupt. On the CH32V003/6,
there is one group of 8 lines, while on the CH32V208 there are
multiple groups with between one and six lines per group.
In the same way as the STM32 and GD32, define an EXTI driver that
configures the peripheral and an internal interface that can configure
individual lines.
Signed-off-by: Michael Hope <michaelh@juju.nz>
RA8P1 has 14 ports (from 0 to d) and 32 external irq while current
driver support 12 ports (0 to b) and 16 external irq.
This add addtional support for remain ports and external irq to be
able to work with RA8P1.
Fix the lack condition GPIO_RA_IOPORT for GPIO_RA_HAS_VBTICTLR
config
Signed-off-by: Thao Luong <thao.luong.uw@renesas.com>
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
