Add device tree for Intel SoC FPGA Agilex initial bring up. This is the
first version of device tree which enable single CPU core and basic
drivers that needed by hello_world example.
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
The shared multi-heap memory pool manager uses the multi-heap allocator
to manage a set of reserved memory regions with different capabilities /
attributes (cacheable, non-cacheable, etc...) defined in the DT.
The user can request allocation from the shared pool specifying the
capability / attribute of interest for the memory (cacheable /
non-cacheable memory, etc...)
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Add specific properties to enable remap for PA11/PA12, which is a
possibility on STM32G0/F0 SoCs.
These properties only have effect when defined.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This name should be the same as cpus node in dtsi. After the power
policy is added, the cpu-power-states in the CPU properties can
be used.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
AHB prescaler is a value which divides the SYSCLOCK
to provide the HCLK. The HCLK supplies the core, AHB bus, memory.
On the stm32wb and stm32wl, the HCLK for CPU1 is HCLK1
with cpu1-prescaler.
By default the value is 1, else the HCLK must be correctly set.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
interrupt controller, also places its relevant
peripheral sources allowing drivers to use the
DT macros instead of espressif headers.
Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
This reverts commit d3a558591f.
We shouldn't be adding vendor prefixes for things we don't have
upstream bindings for unless we've inherited them from Linux.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
If supported by the SPI instance and soc, this property will
configure the frame-format to be compliant with the TI mode.
By default, if supported, the frame-format is Motorola mode.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The maximum supported speed according to the SX126x datasheet (I have
not found that information in the STM32WL datasheet or reference
manual). Increase the Sub-GHz SPI frequency from 1 Mhz to to 12 MHz,
which corresponds to a baud rate prescaler of 4 with a 48 MHz clock. It
also matches what is done the the STM32CubeWL package.
This reduces the time the MCU is kept running, thus reducing the global
power consumption.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This adds the uart4 device to the stm32f3_disco board
based on the stm32f303 device from STMicroelectronics
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit adds stm32f103xd series dts file that was missing.
Also, changed stm32f103xe.dts for highlighting the differences between
f103xd and f103xe series.
Signed-off-by: Deimantas Aukštkalnis <deimantas.aukstkalnis@teltonika.lt>
Add DT bindings for the optional Interrupt Translation Service module
of the ARM GICv3 Interrupt Controller.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Implements a shim layer driver using st hal for
I3G4250D gyro, mounted for example on stm32f3_disco_E.
No support for triggers included yet.
Signed-off-by: Jonathan Hahn <Jonathan.Hahn@t-online.de>
1. Add support for multiple syscon entries (as a side effect, this also
fixed syscon.c implementations which weren't being linked to their
syscon.h counterparts).
2. Add support for different width registers in syscon.
3. Add tests for syscon
Signed-off-by: Yuval Peress <peress@chromium.org>
Since version 1.11.0, Full stack M0 binary requires 216K of flash
being available, while previously 212K were required.
Review flash partitioning to take it into account.
Additionally:
- update value in board yaml file.
- align value in package .dtsi file
Fixes#38735
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The NPCX I2C implementation contains two modules, an I2C port and an
I2C controller. Disable the I2C controller nodes by default and require
the user to enable both the I2C port and controller in the devicetree.
Signed-off-by: Keith Short <keithshort@google.com>
Fix a typo bug where sercom5 pinctrl has pad2 and pad3
has duplicated pads for pb0/pb2 and pb1/pb3.
Per the datasheet, pb2 and pb3 should be pad0 and pad1 respectively.
Signed-off-by: Ron Smith <rockyowl171@gmail.com>
TWIM peripherals cannot perform write transactions from buffers
located in flash. The content of such buffers needs to be copied
to RAM before the actual transfer can be requested.
This commits adds a new property (zephyr,flash-buf-max-size) that
informs the driver how much space in RAM needs to be reserved for
such copying and adds proper handling of buffers located in flash.
This fixes an issue that caused that e.g. the DPS310 sensor driver
did not work on nRF SoCs that only have TWIM, not TWI peripherals.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Issue an error logging message when the i2c_nrfx_twim driver lacks
a concatenation buffer big enough to properly handle a call to
i2c_burst_write() function, to give the user a hint what is wrong.
Also use by default a 16-bytes long concatenation buffer for every
instance of the i2c_nrfx_twim driver. Such value should cover most
of the simple uses of the i2c_burst_write() function, like those
in the stmemsc sensor drivers, and when a longer buffer is needed,
the user will be provided with the above message pointing to the
property that should be adjusted.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Remove the HL7800 DTR device tree binding because the
DTR IO is not needed for operation of the HL7800
modem.
Signed-off-by: Ryan Erickson <ryan.erickson@lairdconnect.com>
This patch fixes wrong PLIC irq number of UART and SPI for SiFive
FU740 on HiFive Unmatched. Use samples/subsys/console/echo for
testing.
Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
The priority of the LPTim interrupt on each stm32 soc
is put at the same level as the SysTick. This priority
level is given by the system Handler priority reg
(SHPR3) when the PM is not configured.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
stm32f411 includes stm32f401 which do already correctly define spi4
The definition in stm32f411 was missing a clock attribute
Signed-off-by: Kim Bøndergaard <kim.boendergaard@escoglobal.com>
stm32f410, stm32f411 and stm32f412 enable the SPI5 device with
bit 20 on the APB2 clock
Signed-off-by: Kim Bøndergaard <kim.boendergaard@escoglobal.com>
