Commit Graph

21 Commits

Author SHA1 Message Date
Gerard Marull-Paretas
6810a53297 twister: s/riscv(32|64)/riscv
Only riscv is supported now, any 32/64-bit requirements need to use
CONFIG_64BIT now.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-02-26 12:49:06 +01:00
Huifeng Zhang
1cec85dc07 tests: kernel: fpu_sharing: Enable it on VFP platfrom of aarch32
- Remove raising compilation error in `float_regs_arm_gcc.h`
    These macros are checked in 'load_store.c', so no need to check them
    again in 'float_regs_arm_gcc.h'

- Enable this test on the VFP platform of aarch32

Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
2023-06-21 16:06:08 +02:00
Anas Nashif
b835b02136 tests: cleanup metadata and filtering
- Add integration_platforms to avoid excessive filtering
- Make sure integration platforms are actually part of the filter
- Fix some tags and test meta data

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2023-06-13 09:38:27 -04:00
Gerard Marull-Paretas
93b63df762 samples, tests: convert string-based twister lists to YAML lists
Twister now supports using YAML lists for all fields that were written
as space-separated lists. Used twister_to_list.py script. Some artifacts
on string length are due to how ruamel dumps content.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2023-05-10 09:52:37 +02:00
Keith Packard
e17191b146 tests/fpu_sharing: Increase main stack size on riscv64
Looks like switching the main return value to int means that stack
frame persists and increases stack usage by a few bytes. Increase the
main stack size to avoid overflows.

Signed-off-by: Keith Packard <keithp@keithp.com>
2023-04-14 07:49:41 +09:00
Lucas Tamborrino
9e4d1a817c tests: kernel: fpu_sharing: generic: add xtensa testing
Add xtensa arch to FPU test.

Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
2023-04-08 12:34:25 +02:00
Kumar Gala
d31814e990 tests: Fix floating point test variants on x86 w/LLVM
LLVM doesn't support SSE + 387 math.  As such if SSE is enabled we
have to utilize SSE floating point.  To utilize 387 math, SSE has
to be disabled.

Update the floating point related tests to introduce 387 only variants
that will build on both GCC & LLVM based tools.  Than we exclude llvm
based (llvm, oneApi) toolchains from the CONFIG_X86_SSE_FP_MATH=n and
CONFIG_X86_SSE=y test variants.

Signed-off-by: Kumar Gala <kumar.gala@intel.com>
2023-02-21 08:25:38 -05:00
Anas Nashif
ba7d730e9b tests/samples: use integration_plaforms in more tests/samples
integration_platforms help us control what get built/executed in CI and
for each PR submitted. They do not filter out platforms, instead they
just minimize the amount of builds/testing for a particular
tests/sample.
Tests still run on all supported platforms when not in integration mode.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-11-29 16:03:23 +01:00
Julius Barendt
e54cc1f6d1 tests: fpu_sharing/generic: Remove qemu_leon3 workaround
This workaround is no longer needed as sparc stack footprint
is reduced in this commit:
5cf2083e8b87f918a522423a1659ae58137ceea0

Signed-off-by: Julius Barendt <julius.barendt@gaisler.com>
2022-08-03 12:05:49 +02:00
Guo Lixin
d6995cb050 tests: fpu_sharing/generic: workaround crash on qemu_leon3
When running tests/kernel/fpu_sharing/generic on qemu_leon3 with the
new ztest API, a fatal error is raised while test is reported success.
So workaround this by changing the main stack size to 2048.

Signed-off-by: Guo Lixin <lixinx.guo@intel.com>
2022-07-18 12:20:39 -04:00
Bradley Bolen
90b1c6a3e8 tests: fpu_sharing: Enable support for Cortex-R
Reuse the Cortex-M paths for testing the floating point unit.

Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
2022-05-05 12:03:27 +09:00
Ioannis Glaropoulos
1a7228a462 tests: add fpu tag the tests which enable FPU and FPU_SHARING options
Introduce the fpu tag to tests that explicitly enable
the FPU and FPU_SHARING Kconfig options. The tag could
be used to run all FPU-related tests in the tree.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2021-06-22 08:45:41 -04:00
Nicolas Pitre
f1f63dda17 arm64: FPU context switching support
This adds FPU sharing support with a lazy context switching algorithm.

Every thread is allowed to use FPU/SIMD registers. In fact, the compiler
may insert FPU reg accesses in anycontext to optimize even non-FP code
unless the -mgeneral-regs-only compiler flag is used, but Zephyr
currently doesn't support such a build.

It is therefore possible to do FP access in IRS as well with this patch
although IRQs are then disabled to prevent nested IRQs in such cases.

Because the thread object grows in size, some tests have to be adjusted.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2021-05-03 11:56:50 +02:00
Eugeniy Paltsev
1b41da2630 ARC: Kconfig: rename CPU_ARCV2 option to ISA_ARCV2
* Rename CPU_ARCV2 to ISA_ARCV2. That helps to avoid conflict between
  CPU families naming and ISAs naming and aligns this options
  with other ARC OSS projects.

* Generalize ARCV2 check to ARC check where it is required.

NOTE: we add ISA_ARCV2 option in a choice list as a preparation
for ISA_ARCV3 addition.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
2021-03-25 07:23:02 -04:00
Daniel Leung
e0fe89cdda tests: fpu_sharing: allow board qemu_x86_lakemont
This adds qemu_x86_lakemont to the platform allow list
for the FPU sharing tests. Since Lakemont supports SSE3
and SSSE3, it is better to test them also.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2021-02-19 18:51:04 -05:00
Daniel Leung
ce44048d46 x86: rename CONFIG_SSE* to CONFIG_X86_SSE*
This adds X86 keyword to the kconfigs to indicate these are
for x86. The old options are still there marked as
deprecated.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2021-02-15 08:21:15 -05:00
Daniel Leung
735c0096ae tests: fpu_sharing: test both FPU and SSE on x86
On x86, it is possible to use FPU (387) and SSE for floating
point operations. So test both.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2021-02-15 08:21:15 -05:00
Martin Åberg
4604c45541 tests: enable and run many tests on RISC-V
This commit enables lots of tests on riscv32 and riscv64 which were
previously disabled.

Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
2021-01-15 13:06:33 -05:00
Martin Åberg
5fc94948a8 tests/fpu_sharing: ported to SPARC
Added the bits and pieces required to run the test on SPARC.

Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
2020-12-04 14:33:43 +02:00
Anas Nashif
dca317c730 sanitycheck: inclusive language
change whitelist -> allow.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2020-08-27 07:04:07 -04:00
Stephanos Ioannidis
004039d08c tests: Rename kernel.fp_sharing
This commit renames the `kernel.fp_sharing` tests to
`kernel.fpu_sharing`, in order to align with the recent
`CONFIG_FP_SHARING` to `CONFIG_FPU_SHARING` renaming.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-05-08 10:58:33 +02:00