Enable all these tests which run in native_posix in native_sim,
Switch from native_posix to native_sim as default test platform
And switch native_posix overlays to native_sim.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Twister now supports using YAML lists for all fields that were written
as space-separated lists. Used twister_to_list.py script. Some artifacts
on string length are due to how ruamel dumps content.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
As both C and C++ standards require applications running under an OS to
return 'int', adapt that for Zephyr to align with those standard. This also
eliminates errors when building with clang when not using -ffreestanding,
and reduces the need for compiler flags to silence warnings for both clang
and gcc.
Most of these changes were automated using coccinelle with the following
script:
@@
@@
- void
+ int
main(...) {
...
- return;
+ return 0;
...
}
Approximately 40 files had to be edited by hand as coccinelle was unable to
fix them.
Signed-off-by: Keith Packard <keithp@keithp.com>
From FPGA-TN-02001-3.3 "iCE40 Programming and Configuration":
> After driving CRESET_B High or allowing it to float High, the AP must
> wait a minimum of 1200 µs, allowing the iCE40 FPGA to clear its internal
> configuration memory.
Signed-off-by: Armin Brauns <armin.brauns@embedded-solutions.at>
FPGA drivers should be built on a regular basis to ensure
that there are no regressions. To that end, the sensors
build_all test was cloned, trimmed-down, and the ice40
driver is built with the two separate devicetree-specified
configurations (load modes).
The first load mode is for regular SPI bitstream flashing
(useful for higher-end microcontrollers with a faster clock).
The second load mode is for bitbanged GPIO bitstream flashing
(useful for lower-end microcontrollers that need to squeeze
every cycle of performance to meet timing requirements for
iCE40 bitstream loading).
Signed-off-by: Chris Friedt <cfriedt@meta.com>
