Currently, if the user wants to allocate heap on external RAM
he needs to enable CONFIG_ESP_SPIRAM and set a threshold defined
with CONFIG_ESP_HEAP_MIN_EXTRAM_THRESHOLD.
This approach requires that we re-implement `k_malloc` and allocate
the memory on the proper region based on the block size.
By using the shared multi heap feature the proccess of allocating
memory from external memory becomes more fluent and simple.
The attribute SMH_REG_ATTR_EXTERNAL was added to reference the
external memory.
Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
Follow ARM architecture recommendations:
* Use Data Synchronization Barrier (DSB) instruction before WFI,
to ensure that pending memory transactions complete before
changing state.
* To guarantee pend interrupts are recognized before subsequent
operation, use ISB after CPSIE (__irq_enable)
This prevents sporadicy delayed ISRs due to continous MEC172x
entering/exiting deep sleep.
Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
Background of this modification is to make clock control
driver code provided by Renesas vendor to support for Renesas MCU
on Zephyr.
Signed-off-by: Quy Tran <quy.tran.pz@renesas.com>
dts: arm: nxp: mimxrt1180_evk: add GPT1/2 instance into devicetree
Enable GPT1/2 clock
Add GPT1/GPT2 instances
Set GPT2 as a counter, the default frequency is 240000000
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
This serves two main purposes:
- change the CPU clock via devicetree nodes
- provide the APB frequency to device drivers via the clock driver
interface
Theoretically this could also support choosing between the available
clock sources, but right now we only support LPOSC0 going into PLL0,
going into AHB.
Turning the PLL back off is also not supported since the only current
use case is to set the PLL frequency, turn it on, and switch the AHB
over to it.
Signed-off-by: Michael Zimmermann <michael.zimmermann@grandcentrix.net>
This is the bare minimum and includes the SoC, pinctrl, flash and
devicetree.
I had to include the flash driver that early because I couldn't make
Zephyr compile without flash driver nodes in the device tree.
Signed-off-by: Michael Zimmermann <michael.zimmermann@grandcentrix.net>
Introduce riscv_clic_irq_vector_set() to implement z_riscv_irq_vector_set()
for CLIC. This commit also introduces CONFIG_CLIC_SMCLICSHV_EXT to indicate
support for the smclicshv extenion and riscv_clic_irq_vector_set().
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
FCB was being relocated to the wrong location, and the flexspi clock
setup was not being relocated.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Add slot type for debug-stream transport over a debug window slot. For
details see src/debug/debug_stream/debug_stream_slot.h under SOF
sources [1].
[1] https://github.com/thesofproject/sof
Signed-off-by: Jyri Sarha <jyri.sarha@linux.intel.com>
ESP32 SoC has multiple revisions, some of which are not supported
by the current implementation, as such as REV0 and REV1. This PR
adds an option to indicate user that this is not recommended and not
supported.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
IMXRT11XX secondary core should not deinit ENET PLL
as it could be configured by primary core.
Signed-off-by: Anders Bjørn Nedergaard <abn@polytech.com>
The nRF9280 is a SiP (System-in-Package) consisting of the nRF9230 SoC
and additional components such as PMIC and others. Additionally,
the nRF9230 contains several CPUs, similarly to the nRF54h20 SoC.
Update nrfx glue, and add necessary Kconfig and initialization code
to allow building for nRF9280 targets: CPU, Radio and PPR cores.
The nRF9280 is used for all user build targets and Kconfigs,
whereas the nRF9230 is used as the build target for the MDK.
Signed-off-by: Emanuele Di Santo <emdi@nordicsemi.no>
Co-authored-by: Andreas Moltumyr <andreas.moltumyr@nordicsemi.no>
Move mpu_region.c to common folder, to re-use with nRF92.
Rename it to nrf54hx_nrf92x_mpu_regions.c to indicate
which product series it applies to.
Signed-off-by: Emanuele Di Santo <emdi@nordicsemi.no>
Move default of monolithic and fw loader, options, etc to the
common kconfig files rather than defaulting in soc file.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Consolidate the ROM RAMLOADER config to be in one place,
add a new Kconfig file to be included by the SOCs with the feature.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
The CONFIG_USB_MCUX_CONTROLLER_TYPE choice config
is not necessary, let's just remove it. Theoretically,
if there was an SOC with the EHCI and LPCIP3511, then
it might cause a build error, but there is no SOC
which is supported on this legacy driver that has that.
Remove all settings of it in the SOC files.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Currently this code related to how to configure the
flash size and address when using flexspi to XIP is copy
pasted in all sort of places and ways all over the tree,
let's clean this up and have single point of control over
this configuration.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Move all dependencies of the family config to series level,
and put a disclaimer saying not to use the family config.
Change all occurrences of the family config in code to the
MCXNX4X series config.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
NXP is not supporting these derivative parts in the zephyr upstream,
these references to them should therefore be removed in order to avoid
confusion.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
The Kconfig defaults should be in Kconfig.defconfig.
MFD should not be made dependent on the LP flexcomm being
enabled, since MFD can be for other things than just flexcomm.
Change from depends on to an if.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Doesn't seem like there is any reason to be changing the
serial and ADC driver init priorities in the SOC defconfigs.
By default, clock control has priority 30, dma has priority 40,
and serial/adc have priority 50. This seems already to be the order
that is needed, and the original goal of these overrides, which
don't seem necessary anymore.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
There are some SOCs which use the same pinctrl
device, but are not really overall that similar to the kinetis
family of SOCs, so prepare to reuse this code by other SOC families.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Moving RT118x kconfigs to series level instead of family level,
and cleaning up redundant declarations, and adding missing
HAS_MCUX_FLEXSPI selection.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
/zephyr/soc/intel/intel_adsp/ace/power.c:46:9: warning: implicit
declaration of function 'cache_data_flush_range'; did you mean
'sys_cache_data_flush_range'? [-Wimplicit-function-declaration]
46 | cache_data_flush_range((__sparse_force void *)
| ^~~~~~~~~~~~~~~~~~~~~~
| sys_cache_data_flush_range
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
The symbol DCACHE_LINE_SIZE was not being defined in Intel ADSP
targets.
It fixes the following problem:
/zephyr/soc/intel/intel_adsp/ace/power.c:30:29: error:
'CONFIG_DCACHE_LINE_SIZE' undeclared here (not in a function); did you
mean 'XCHAL_DCACHE_LINESIZE'? 30 | uint8_t
adsp_pending_buffer[CONFIG_DCACHE_LINE_SIZE]
__aligned(CONFIG_DCACHE_LINE_SIZE);
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Add missing braces to comply with MISRA C:2012 Rule 15.6 and
also following Zephyr's style guideline.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
The Audio integration PLL is faster on PTL compared to earlier ACE
platforms: 442.368 MHz instead 393.216 MHz, however the default
divider remained 16, which will result incorrect cardinal clock speed.
Change the divider to 18 in order to get correct 24.576 MHz cardinal
clock.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
Add initial support for nuvoton npcm400, which is a chip
family of Satellite Management Controller(SMC).
Add ecst python scripts to append the header used by ROM Code
Signed-off-by: Tyrone Ting <kfting@nuvoton.com>
Signed-off-by: James Chiang <cpchiang1@nuvoton.com>
Signed-off-by: Joseph Liu <kwliu@nuvoton.com>
Enable the NXP Kinetis Low Power Timer (LPTMR) timer driver when
power management is enabled.
When the NXP KE1xZ SoC series is using the Arm SysTick as hardware
timer, the cycles/second will always be equal to the CPU core clock
frequency.
Signed-off-by: Anke Xiao <anke.xiao@nxp.com>
Add support for the stm32h755 which is a close relative of
the stm32h745 with additional cryptography and hashing
peripherals.
Signed-off-by: Mike Banducci <michael.banducci@sandc.com>
Background of this modification is to make clock control
driver code provided by Renesas vendor to support for Renesas MCU
on Zephyr.
Signed-off-by: Quy Tran <quy.tran.pz@renesas.com>
- Initial support for RA6M2 SoC
Signed-off-by: Tri Nguyen <tri.nguyen.wj@bp.renesas.com>
Signed-off-by: Danh Doan <danh.doan.ue@bp.renesas.com>
Signed-off-by: Duy Phuong Hoang. Nguyen <duy.nguyen.xa@renesas.com>
Update pinctrl driver which used for Renesas RA series with
PFS secure register
Signed-off-by: Duy Phuong Hoang. Nguyen <duy.nguyen.xa@renesas.com>
Signed-off-by: Quy Tran <quy.tran.pz@renesas.com>
Add support of sys_poweroff API on m2l31x series.
It could support SPD0~2 standby or DPD0~1 deep power down mode.
Signed-off-by: cyliang tw <cyliang@nuvoton.com>
Enable the driver using the standard mechanism used everywhere else in
the tree. It is possible here as it is a singleton, so there's no
dependency on nrfx instantiation magic.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Add new RT118x device, due to structure is different from rt11xx series.
Boot header also differ from rt10xx and rt11xx, so add support for boot
container.
define new container name and new container tag
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
Let's link from the deprecated instructions.
To increase visibility and hopefully avoid developers forgetting to
do so.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Now that the dts/bindings filter has been removed from
Devicetree Binding area, this area serves no real purpose.
Move the include/dt-bindings files to their respective areas.
Fix some of the orphaned dts/bindings paths.
Add regex filter for any binding with "zephyr" in the name to be
in the devicetree area.
Fix the imx_spc.h file being in it's own pm/ folder instead of
power/ like the other power related headers.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
XTENSA_CCOUNT_HZ is no longer common to ACE soc series
This will fix Hz value for ACE30 platform
Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
The Host Interface Type in the DEVCNT register sets the HIF type
(either eSPI or LPC).
Currently, it is configured in the host-interface-related drivers like
eSPI or SHI. However, some I/O pads sourced from VHIF in the other
modules such as GPIO and I3C also rely on this field. It might be
problematic when using those I/Os without enabling eSPI or SHI drivers.
This commit moves the setting from the specific drivers to the global
system initialization function scfg_init().
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Initial commit to suppor RA8D1 SoC
This is deveop base on RA8M1 so it will have similar stucture and
feature
Signed-off-by: Duy Phuong Hoang. Nguyen <duy.nguyen.xa@renesas.com>
Some new Nordic nRF SoCs are based on a common platform, named
'Haltium'. Introduce a selectable Kconfig option available for series to
flag they are part of such common platform. This will allow to easily
enable common code shared across all Haltium based products.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
RA4M1-specific options were being applied system-wide because
conditions were not set properly.
This change fixes this problem.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Instead of forcing users to provide this setting, allow to describe
which signals require CLOCKPIN enablement at device nodes. This is later
captured by the pinctrl macros and applied in the pinctrl driver. Note
that name has been adjusted to nordic,clockpin-enable to avoid confusion
with clock related settings.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
custom arch_cpu_idle and arch_cpu_atomic_idle implementation was done
differently on different architectures. riscv implemented those as weak
symbols, xtensa used a kconfig and all other architectures did not
really care, but this was a global kconfig that should apply to all
architectures.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Add config file to host WiFi specific settings.
Introduce CONFIG_ESP_WIFI_MAX_THREAD_PRIO to be used
as a cap for the LL driver runtime.
Signed-off-by: Marek Matej <marek.matej@espressif.com>
The power_down() function will lock dcache for the hpsram_mask
array. On some platforms, the dcache lock will fail if the array
is on cache line that can be used for window register context
saves.
Work around this by aligning and padding the hpsram_mask to cacheline
size.
Link: https://github.com/thesofproject/sof/issues/9268
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
After flashed EC image, we needed to manually press the reset button
on it8xxx2_evb. Now, without pressing the button, we can disable
debug mode and trigger a watchdog hard reset for running tests.
After flash EC, running below tests can pass (without pressing the button):
west build -p always -b it8xxx2_evb tests/drivers/watchdog/wdt_basic_api
west build -p always -b it8xxx2_evb tests/kernel/timer/timer_api
west build -p always -b it8xxx2_evb tests/kernel/fatal/exception
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
For stm32 platforms where the sysclock is less or equal to
32MHz, the Ticks per second is reduced to 8000 (instead of
10000).
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Many xtensa target jump from soc code directly into cstart and depend on
architecture code being initialized in arch_kernel_init(). Instead of
jumping to cstart, jump to newly introduced prep_c similar to all other
architectures, where common platfotm initialization will happen.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This update is to support clock API for RA8
Move the clock initialize function into clock driver
Peripheral clock now has 2 more property in clock cell for enable
and disable clock to peripheral module
Signed-off-by: Duy Phuong Hoang. Nguyen <duy.nguyen.xa@renesas.com>
This change adds the device tree property for specifying oe-override
(output-enable override behavior), as well as defines for possible values
of the property.
RP2040 GPIOs can be configured to automatically invert the output-enable
signal from the selected peripheral function. This is useful for tasks like
writing efficient PIO code, such as in the i2c example in the rp2040
datasheet.
Signed-off-by: Yiding Jia <yiding.jia@gmail.com>
cplusplus-rom linker initialization was wrongly placed
in RAM area when it should be in ROM area.
Fixes#75853
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
In addition to Kconfig options (soon to be deprecated), allow
configuring the regulators using DT.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Previously, the `soc.c` files for the IMXRT11xx, IMXRT5xx/CM33, and
IMXRT6xx/CM33 did not register the log module. This caused build
errors when DEBUG logging was enabled, as the `power.c` file attempted
to access a non-existent SOC log module for debug messages.
This commit fixes the issue by registering the log module in the
`soc.c` files for the specified SoCs, thereby resolving the build
errors.
Signed-off-by: Apoorv Singh <apoorv.singh@gin.de>
Fix formatting for `soc.c` files for the IMXRT11xx, IMXRT5xx/CM33, and
IMXRT6xx/CM33 by running 'clang-format'.
Signed-off-by: Apoorv Singh <apoorv.singh@gin.de>
Convert NXP System Timer Module driver to a native driver.
Timer prescaler in tests is updated because short relative alarms
sometimes give false positives.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Allow developer to use the baremetal Bluetooth functionalities of the
CC13X2 and CC26X2 series SoCs without having to use the full Zephyr
Bluetooth stack.
Signed-off-by: Benedikt Streicher <streicher.b@posteo.de>
Convert NXP SWT watchdog driver to a native driver and extend the
SWT supported functionalities and configuration options.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Convert power management to native drivers retaining existing
functionalities. Presently only SoC reset support and power control
initialization is supported, but these drivers will be extended to
support power management as well.
MC_ME and MC_RGM peripherals are common enough to be reused by other NXP
S32 devices, whereas PMC has specific implementations for each SoC
series.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Allow CONFIG_NRF_APPROTECT_LOCK and
CONFIG_NRF_SECURE_APPROTECT_LOCK with TF-M with all the SOC's
that support TF-M.
Signed-off-by: Markus Lassila <markus.lassila@nordicsemi.no>
Split SIUL2 instance index for the MSCR and IMCR registers as required
by some pins. Pinmux macros definitions in hal_nxp must be updated
accordingly.
Fixes#76147
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
It seems this SiP variant is not sold by espressif directly, but it is
used by the Odroid Go. The Odroid Go documentation calls this a "custom"
model [1].
There already exists a SiP specific device tree include file:
zephyr/dts/xtensa/espressif/esp32/esp32_wrover_e_n16r4.dtsi
[1] https://wiki.odroid.com/odroid_go/odroid_go#specifications
Signed-off-by: Gero Schwäricke <gero.schwaericke@posteo.de>
DMM shall be initialized as early as possible to allow drivers to
use it. For example, uart may need it early since it starts
RX during initilization in some configurations.
Making dmm_init() public and calling it in soc init function.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Add support of sys_poweroff API on m46x series.
It could support SPD standby or DPD deep power down mode.
Signed-off-by: cyliang tw <cyliang@nuvoton.com>
Remove the ‘HAS_MCUX_ACMP’ Kconfig, and also remove it from
driver and soc Kconfig files. It is not needed since we already
depend on 'ACMP' enabled in the dt file, the 'HAS_MCUX_ACMP'
kconfig is a relic of the past before devicetree was stable.
Signed-off-by: Anke Xiao <anke.xiao@nxp.com>
When not using BT, users may want to enable the cpunet core. Until now,
this has been done at board level (so duplicating unnecessary code)
using CONFIG_BOARD_ENABLE_CPUNET. The board-level options were usually
enabled automatically for BT, however, this was unnecessary as BT driver
already takes care of the setup.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Convert pin control, GPIO and external interrupt controller drivers
based on SIUL2 peripheral to native drivers. This must be done in a
single commit to preserve atomicity, as these drivers depend on each
other.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
The total number of IRQs for this chip is 110.
Refer to the reference manual table 46 for IRQs.
Signed-off-by: Rahul Arasikere <arasikere.rahul@gmail.com>
Place zephyr library in ILM. This can improve performance.
test:
Print the message 10000 times with 1ms sleep interval to compare the
time difference before and after adding RAM code on the it82002bw evb.
RAM code size save time
original: 1954 bytes
libzephyr.a: +16974 bytes -608ms
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Place kernel library in ILM. This can improve performance.
test:
Print the message 10000 times with 1ms sleep interval to compare the
time difference before and after adding RAM code on the it82002bw evb.
RAM code size save time
original: 1954 bytes
libkernel.a: +8941 bytes -649ms
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Place serial library in ILM. This can improve performance.
test:
Print the message 10000 times with 1ms sleep interval to compare the
time difference before and after adding RAM code on the it82002bw evb.
RAM code size save time
original: 1954 bytes
libdrivers__serial.a: +2282 bytes -226ms
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Initialize TCM and SRAM contents only after a destructive reset (e.g.
PoR reset). SRAM retains content during functional reset through a
hardware mechanism, therefore accesses do not cause content
corruption errors.
Fixes#75912
Signed-off-by: Manuel Argüelles <marguelles.dev@gmail.com>
In S32K1 devices, Arm Systick clock frequency is equal to the
CPU core clock frequency, and its value can be obtained from
devicetree.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Currently the code suggests, that setting the SRAM disabling mask to
0 skips powering off SRAM, whereas in fact it's the address of the
mask variable that's checked for NULL. Make this consistent and let
platforms select whether SRAM power down should be selected.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
The IMR is used by the firmware to hold its own copy for hot-booting
and for an "L3 heap," used for slow large allocations like loadable
libraries. The beginning of the L3 heap is currently hard-coded and
now the firmware has grown too large to fit into the dedicated area
so that it gets overwritten by heap allocations. This is a critical
bug that needs an urgent solution, for which we increase the offset,
but a real fix must calculate the L3 heap offset automatically.
BugLink: https://github.com/thesofproject/sof/issues/9308
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
After recent nsim SoCs & boards reorganization the SOC_SERIES_*
config is missing for vpx5 SoC which leads to cmake errors
when building against nsim/nsim_vpx5 configuration.
Fix that and align soc series name in soc.yml
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
The source files required for this features are not present
in the tree for this SOC.
So if CONFIG_PM or CONFIG_POWEROFF are enabled, there would
be a cmake failure.
Let's just indicate these features are not supported in
kconfig.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
