On platforms with enforced memory access modes, .text is read-only.
Move hpsram_mask to a cached data section to fix PTL.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
This patch addresses an issue in the ACE platform power management code
where the HST domain suspend operation was performed after the IMR
context save. This resulted in the power management context being
restored with outdated values upon wake-up from D3 state, leading to a
failure to resume the HST domain correctly.
By moving the `pm_device_runtime_put(INTEL_ADSP_HST_DOMAIN_DEV)` call
before the IMR context save, we ensure that the HST domain is suspended
with the current context, and upon resume, the power management context
has the correct information to restore the HST domain state.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Add missing braces to comply with MISRA C:2012 Rule 15.6 and
also following Zephyr's style guideline.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Assembly in power_down() in power_down.S already defines data and
code to be locked in cache when powering down SRAM. Instead of adding
another such location in power.c, move the hpsram_mask[] array into
power_down.S. This fixes hard to debug failures when shutting down
the ADSP.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
This commit introduces a new Kconfig option `CONFIG_SRAM_RETENTION_MODE`
that allows the configuration of SRAM retention mode during the
initialization phase of the firmware boot-up process. By default, the
retention mode is enabled to maintain the existing behavior. However,
this option provides the flexibility to disable the retention mode if
needed, without modifying the Zephyr codebase.
The SRAM initialization functions `hp_sram_init` and `lp_sram_init` in
`sram.c` have been updated to conditionally set the retention mode based
on the value of this Kconfig option.
Additionally, an unused macro `DELAY_COUNT` has been removed from
`sram.c` to clean up the code.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
/zephyr/soc/intel/intel_adsp/ace/power.c:46:9: warning: implicit
declaration of function 'cache_data_flush_range'; did you mean
'sys_cache_data_flush_range'? [-Wimplicit-function-declaration]
46 | cache_data_flush_range((__sparse_force void *)
| ^~~~~~~~~~~~~~~~~~~~~~
| sys_cache_data_flush_range
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Add missing braces to comply with MISRA C:2012 Rule 15.6 and
also following Zephyr's style guideline.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
The Audio integration PLL is faster on PTL compared to earlier ACE
platforms: 442.368 MHz instead 393.216 MHz, however the default
divider remained 16, which will result incorrect cardinal clock speed.
Change the divider to 18 in order to get correct 24.576 MHz cardinal
clock.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
XTENSA_CCOUNT_HZ is no longer common to ACE soc series
This will fix Hz value for ACE30 platform
Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
The power_down() function will lock dcache for the hpsram_mask
array. On some platforms, the dcache lock will fail if the array
is on cache line that can be used for window register context
saves.
Work around this by aligning and padding the hpsram_mask to cacheline
size.
Link: https://github.com/thesofproject/sof/issues/9268
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Currently the code suggests, that setting the SRAM disabling mask to
0 skips powering off SRAM, whereas in fact it's the address of the
mask variable that's checked for NULL. Make this consistent and let
platforms select whether SRAM power down should be selected.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
The IMR is used by the firmware to hold its own copy for hot-booting
and for an "L3 heap," used for slow large allocations like loadable
libraries. The beginning of the L3 heap is currently hard-coded and
now the firmware has grown too large to fit into the dedicated area
so that it gets overwritten by heap allocations. This is a critical
bug that needs an urgent solution, for which we increase the offset,
but a real fix must calculate the L3 heap offset automatically.
BugLink: https://github.com/thesofproject/sof/issues/9308
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
A recent commit fb53d2ef8d ("ace: power: replace pseudo-assembly
movi") contained a bug: the Xtensa "movi" assembly instruction must
be written with the immediate argument already shifted left by 8, the
compiler doesn't do that automatically. This still somehow worked on
MTL but failed on LNL. Fix both occurrences.
Fixes: #75700
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
When switching off memory banks we cannot use movi with arbitrary
immediate arguments, they will be converted by the compiler to memory
accesses. Only constants within the allowed range should be used.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
The power_down() function attempts to lock the hpsram_mask on-stack
variable in data cache, which causes an exception. Moving it to .bss
by making it static fixes it.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Replace the MMU initialization call with the new MMU re-initialization
API during the core context restore process in the ACE power management
code.
The previous code was directly calling `xtensa_mmu_init()` upon
restoring the core context, which is not appropriate when the MMU
context may have been preserved during low-power states. The new
`xtensa_mmu_reinit()` API is designed to re-establish the MMU context
without overwriting the existing page table, ensuring that any runtime
changes to the MMU configuration are retained.
Changes made in this patch:
- Removed the call to `xtensa_mmu_init()` from the
`_restore_core_context()` function.
- Added a call to `xtensa_mmu_reinit()` after restoring the
miscellaneous registers.
This update aligns the ACE power management code with the correct MMU
handling procedures when recovering from low-power states, as per the
recent changes in the Xtensa MMU support.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This patch updates the power control and status register bitfield
definitions in the ACE30 PTL ADSP power management header to match the
documented hardware specifications. The previous definitions contained
discrepancies that did not align with the actual hardware layout,
potentially leading to incorrect assumptions and usage within the
firmware.
Changes made in this patch:
- Renamed 'rsvd0' to 'rsvd4' to accurately represent the reserved bits
starting at bit position 4.
- Removed the 'rsvd6' field, which was incorrectly defined and is not
present in the hardware register layout.
- Adjusted the bit widths for 'ioxpgs' and 'mlpgs' to correctly reflect
the number of bits these fields occupy in the hardware.
- Introduced a new 'rsvd15' field in both 'ace_pwrctl2' and
'ace_pwrsts2' structures to account for the remaining reserved bits,
ensuring the structure sizes accurately represent the full register
width.
By correcting these bitfield definitions, the firmware's power
management code will now be consistent with the actual hardware design,
improving reliability and maintainability of the codebase.
Signed-off-by: Ievgen Ganakov <ievgen.ganakov@intel.com>
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Currently iterable sections as per the documentation are added with
zephyr_linker_sources(SECTIONS ...) after bss/noinit.
This commit allows putting sections after common-rom.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
adsp_memory.h is pretty much the same for all ace platforms.
Generalize it getting register address from devicetree and
and move it to a common place.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Platforms that support IPIs allow them to be broadcast via the
new arch_sched_broadcast_ipi() routine (replacing arch_sched_ipi()).
Those that also allow IPIs to be directed to specific CPUs may
use arch_sched_directed_ipi() to do so.
As the kernel has the capability to track which CPUs may need an IPI
(see CONFIG_IPI_OPTIMIZE), this commit updates the signalling of
tracked IPIs to use the directed version if supported; otherwise
they continue to use the broadcast version.
Platforms that allow directed IPIs may see a significant reduction
in the number of IPI related ISRs when CONFIG_IPI_OPTIMIZE is
enabled and the number of CPUs increases. These platforms can be
identified by the Kconfig option CONFIG_ARCH_HAS_DIRECTED_IPIS.
Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
headers for dmic are now part of the SoC and maintained per generation,
so create one header for PTL and build the code for PTL in some of the
drivers (dmic_nhlt).
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit adds definition of ACE 3.0 Panther Lake board.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
power_down() expects a cached pointer. Fix the sparse annotation
to match the implementation (sys_cache_cached_ptr_get() returns a cached
pointer so this is correct).
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
This commit introduces support for an alternate linking method in the
LLEXT subsystem, called "SLID" (short for Symbol Link Identifier),
enabled by the CONFIG_LLEXT_EXPORT_BUILTINS_BY_SLID Kconfig option.
SLID-based linking uses a unique identifier (integer) to identify
exported symbols, instead of using the symbol name as done currently.
This approach provides several benefits:
* linking is faster because the comparison operation to determine
whether we found the correct symbol in the export table is now an
integer compare, instead of a string compare
* binary size is reduced as symbol names can be dropped from the binary
* confidentiality is improved as a side-effect, as symbol names are no
longer present in the binary
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
Secondary cores are not allowed to be power gated on
runtime-idle. They have to explicitely set off by host command.
Remove this state from secondary CPUs so power management logic
does not need workarounds to enforce this behavior.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Corrected virtual memory size to match the range supported by the
Translation Lookup Buffer. The TLB size is 16 MB, however the first 128 KB
is dedicated to LPSRAM and bypasses the TLB. This was taken into account in
KERNEL_VM_BASE, so KERNEL_VM_SIZE was reduced accordingly.
Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
This commit updates the device tree and memory header file
for the Intel MTPM 1.5 platform to define the LSBPM and
HSBPM registers.
Changes include:
- Added node definitions for 'lsbpm' and 'hsbpm' in
intel_adsp_ace15_mtpm.dtsi
- Updated adsp_memory.h
Signed-off-by: Damian Nikodem <damian.nikodem@intel.com>
This commit updates the device tree and memory header file
for the Intel LNL 2.0 platform to define the LSBPM and
HSBPM registers.
Changes include:
- Added node definitions for 'lsbpm' and 'hsbpm' in
intel_adsp_ace20_lnl.dtsi
- Updated adsp_memory.h
Signed-off-by: Damian Nikodem <damian.nikodem@intel.com>
A workaround to avoid icache corruption was added in commit be881d4cf2
("arch: xtensa: add isync to interrupt vector").
This patch implements a different workaround by adding custom logic to
idle entry on affected Intel ADSP platforms. To safely enter "waiti"
when clock gating is enabled, we need to ensure icache is both unlocked
and invalidated upon entry.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Fix the inline documentation to match implementation. As IPFL is used,
the correct matching function is xthal_icache_region_lock().
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Fixes the following errors when sparse (SCA) is enabled:
soc/intel/intel_adsp/ace/power.c:46:12: warning:
cast removes address space '__cache' of expression
/soc/intel/intel_adsp/ace/power.c:48:9: warning:
incorrect type in argument 1 (different address spaces)
Fixes#70725
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Issue an upstream read transaction through uncached memory to flush
out all pending transactions before power down the host domain.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
This patch updates the power status register bitfield definitions in the
power management header for the Intel ADSP ACE 2.0 LNL platform.
Modifications include:
- Adjusting the 'ioxpgs' field from 4 bits to 2 bits.
- Adding a 'rsvd11' field with 2 bits to reflect reserved space.
- Changing the 'mlpgs' field from 2 bits to 1 bit.
- Updating the 'rsvd14' field from 1 bit to 2 bits for alignment.
These changes ensure that the power status register bitfields match the
latest hardware specification for the ACE 2.0 LNL SoC, which is crucial
for accurate power domain status monitoring.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
In case the core is not power gated, waiti will restore intlevel. In
this case we lock interruption after it.
In the bug scenario, the host starts streaming and via SOF APIs, keeps a
lock to prevent Zephyr from entering PM_STATE_RUNTIME_IDLE. During the
test case, host removes this block and core0 is allowed to enter IDLE
state.
When core0 enters power gated state, interrrupts are left enabled (so
the core can be woken up when something happens). This leaves a race
where suitably timed interrupt will actually block entry to power gated
state and k_cpu_idle() in power_gate_entry() will return. This is rare,
but happens often enough that the relatively short test plan run on SOF
pull-requests will trigger this case.
Fixes#69807
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
z_mp_entry() and power_gate_exit() are only called from assembly code
in the same file, where they're defined. Make them "static" and add
an attribute to let the compiler know, that they aren't unused.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
This enables the use of CONFIG_XTENSA_MORE_SPIN_RELAX_NOPS to
specify how many NOPs for arch_spin_relax(). This is to keep
the atomic_cas() (via s32c1i) from saturating the internal bus
with contant RCW ops. The numbers should be further tuned
for specific application but these should provide a good start.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
