cavs15, cavs18 and cavs20 were removed from Zephyr there is no
need to handle those platforms in the tool.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
On platforms with enforced memory access modes, .text is read-only.
Move hpsram_mask to a cached data section to fix PTL.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
This patch addresses an issue in the ACE platform power management code
where the HST domain suspend operation was performed after the IMR
context save. This resulted in the power management context being
restored with outdated values upon wake-up from D3 state, leading to a
failure to resume the HST domain correctly.
By moving the `pm_device_runtime_put(INTEL_ADSP_HST_DOMAIN_DEV)` call
before the IMR context save, we ensure that the HST domain is suspended
with the current context, and upon resume, the power management context
has the correct information to restore the HST domain state.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Add missing braces to comply with MISRA C:2012 Rule 15.6 and
also following Zephyr's style guideline.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Assembly in power_down() in power_down.S already defines data and
code to be locked in cache when powering down SRAM. Instead of adding
another such location in power.c, move the hpsram_mask[] array into
power_down.S. This fixes hard to debug failures when shutting down
the ADSP.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
This commit introduces a new Kconfig option `CONFIG_SRAM_RETENTION_MODE`
that allows the configuration of SRAM retention mode during the
initialization phase of the firmware boot-up process. By default, the
retention mode is enabled to maintain the existing behavior. However,
this option provides the flexibility to disable the retention mode if
needed, without modifying the Zephyr codebase.
The SRAM initialization functions `hp_sram_init` and `lp_sram_init` in
`sram.c` have been updated to conditionally set the retention mode based
on the value of this Kconfig option.
Additionally, an unused macro `DELAY_COUNT` has been removed from
`sram.c` to clean up the code.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
The ringbuffer availability check is subject to race with regards to
update of BF (Buffer Full) and BNE (Buffer Not Empty) bits in DGCS
register, and status of RP (Read Position) and WP (Write Position).
Following sequence is observed without this patch when
calling dma_get_status() on multiple Intel ADSP platforms:
iter 154 pending 1536 RP 768 WP 768, BNE 1, BF 1
-> dma_reload for 384
iter 155 pending 1536 RP 1152 WP 1152, BNE 1, BF 1
-> dma_reload for 384
iter 156 pending 0 RP 0 WP 0, BNE 1, BF 0
Value of pending is not expected to go from 1536 to zero if only 384
bytes have been consumed via dma_reload() since last call to
dma_get_status().
Change the logic to read DGCS register later, after the WP and RP have
been already read, and only check the BNE bit if Read and Write
Positions are equal.
Link: https://github.com/thesofproject/sof/issues/9418
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Co-developed-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
With ACE2/3 the HDA DMA includes registers to read the Linear Link
Position.
Previous platforms (CAVS, ACE1) was able to report the LLP for GPDMA. Since
ACE2 all links are handled with HD-DMA, hence the new register has been
added for the firmware to report the LLP to the host.
Set the total_copied to 0 for older ACE1/CAVS platforms and in case of
host DMA on ACE2/3 since the informatiojn is not available.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
Add slot type for debug-stream transport over a debug window slot. For
details see src/debug/debug_stream/debug_stream_slot.h under SOF
sources [1].
[1] https://github.com/thesofproject/sof
Signed-off-by: Jyri Sarha <jyri.sarha@linux.intel.com>
/zephyr/soc/intel/intel_adsp/ace/power.c:46:9: warning: implicit
declaration of function 'cache_data_flush_range'; did you mean
'sys_cache_data_flush_range'? [-Wimplicit-function-declaration]
46 | cache_data_flush_range((__sparse_force void *)
| ^~~~~~~~~~~~~~~~~~~~~~
| sys_cache_data_flush_range
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
The symbol DCACHE_LINE_SIZE was not being defined in Intel ADSP
targets.
It fixes the following problem:
/zephyr/soc/intel/intel_adsp/ace/power.c:30:29: error:
'CONFIG_DCACHE_LINE_SIZE' undeclared here (not in a function); did you
mean 'XCHAL_DCACHE_LINESIZE'? 30 | uint8_t
adsp_pending_buffer[CONFIG_DCACHE_LINE_SIZE]
__aligned(CONFIG_DCACHE_LINE_SIZE);
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Add missing braces to comply with MISRA C:2012 Rule 15.6 and
also following Zephyr's style guideline.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
The Audio integration PLL is faster on PTL compared to earlier ACE
platforms: 442.368 MHz instead 393.216 MHz, however the default
divider remained 16, which will result incorrect cardinal clock speed.
Change the divider to 18 in order to get correct 24.576 MHz cardinal
clock.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
XTENSA_CCOUNT_HZ is no longer common to ACE soc series
This will fix Hz value for ACE30 platform
Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
The power_down() function will lock dcache for the hpsram_mask
array. On some platforms, the dcache lock will fail if the array
is on cache line that can be used for window register context
saves.
Work around this by aligning and padding the hpsram_mask to cacheline
size.
Link: https://github.com/thesofproject/sof/issues/9268
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Many xtensa target jump from soc code directly into cstart and depend on
architecture code being initialized in arch_kernel_init(). Instead of
jumping to cstart, jump to newly introduced prep_c similar to all other
architectures, where common platfotm initialization will happen.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Currently the code suggests, that setting the SRAM disabling mask to
0 skips powering off SRAM, whereas in fact it's the address of the
mask variable that's checked for NULL. Make this consistent and let
platforms select whether SRAM power down should be selected.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
The IMR is used by the firmware to hold its own copy for hot-booting
and for an "L3 heap," used for slow large allocations like loadable
libraries. The beginning of the L3 heap is currently hard-coded and
now the firmware has grown too large to fit into the dedicated area
so that it gets overwritten by heap allocations. This is a critical
bug that needs an urgent solution, for which we increase the offset,
but a real fix must calculate the L3 heap offset automatically.
BugLink: https://github.com/thesofproject/sof/issues/9308
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
A recent commit fb53d2ef8d ("ace: power: replace pseudo-assembly
movi") contained a bug: the Xtensa "movi" assembly instruction must
be written with the immediate argument already shifted left by 8, the
compiler doesn't do that automatically. This still somehow worked on
MTL but failed on LNL. Fix both occurrences.
Fixes: #75700
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Currently the code in soc.c depends on the MMU of the CPU being enabled,
but this is not enforced. It is thus possible to cause a build error by
manually disabling it (as is required for some LLEXT tests, see #75289).
Make sure this is averted by explicitly selecting ARM_AARCH32_MMU in the
SoC Kconfig.
Signed-off-by: Luca Burelli <l.burelli@arduino.cc>
When switching off memory banks we cannot use movi with arbitrary
immediate arguments, they will be converted by the compiler to memory
accesses. Only constants within the allowed range should be used.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
The power_down() function attempts to lock the hpsram_mask on-stack
variable in data cache, which causes an exception. Moving it to .bss
by making it static fixes it.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Replace the MMU initialization call with the new MMU re-initialization
API during the core context restore process in the ACE power management
code.
The previous code was directly calling `xtensa_mmu_init()` upon
restoring the core context, which is not appropriate when the MMU
context may have been preserved during low-power states. The new
`xtensa_mmu_reinit()` API is designed to re-establish the MMU context
without overwriting the existing page table, ensuring that any runtime
changes to the MMU configuration are retained.
Changes made in this patch:
- Removed the call to `xtensa_mmu_init()` from the
`_restore_core_context()` function.
- Added a call to `xtensa_mmu_reinit()` after restoring the
miscellaneous registers.
This update aligns the ACE power management code with the correct MMU
handling procedures when recovering from low-power states, as per the
recent changes in the Xtensa MMU support.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This patch updates the power control and status register bitfield
definitions in the ACE30 PTL ADSP power management header to match the
documented hardware specifications. The previous definitions contained
discrepancies that did not align with the actual hardware layout,
potentially leading to incorrect assumptions and usage within the
firmware.
Changes made in this patch:
- Renamed 'rsvd0' to 'rsvd4' to accurately represent the reserved bits
starting at bit position 4.
- Removed the 'rsvd6' field, which was incorrectly defined and is not
present in the hardware register layout.
- Adjusted the bit widths for 'ioxpgs' and 'mlpgs' to correctly reflect
the number of bits these fields occupy in the hardware.
- Introduced a new 'rsvd15' field in both 'ace_pwrctl2' and
'ace_pwrsts2' structures to account for the remaining reserved bits,
ensuring the structure sizes accurately represent the full register
width.
By correcting these bitfield definitions, the firmware's power
management code will now be consistent with the actual hardware design,
improving reliability and maintainability of the codebase.
Signed-off-by: Ievgen Ganakov <ievgen.ganakov@intel.com>
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Currently iterable sections as per the documentation are added with
zephyr_linker_sources(SECTIONS ...) after bss/noinit.
This commit allows putting sections after common-rom.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
Modify the winstream code in cavstool.py to use the Regs helper
class and get rid of byte array access when reading and writing
to winstream headers. This brings the cavstool.py implementation
closer to the Zephyr C reference implementation and ensures
the header fields are read and written to with 32bit access.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
intel_adsp_hda_set_buffer() asserts when the HDA buffer is
outside of RAM space. However, it uses CONFIG_SRAM_SIZE as
if it is bytes. In reality, CONFIG_SRAM_SIZE is in KB so
we need to multiply it by 1024, or simply use marco KB().
Fixes#74250
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Also any demand paging and page frame related bits are
renamed.
This is part of a series to move memory management related
stuff out of the Z_ namespace into its own namespace.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This commit enables ISH boards to use APIC timer with TSC time source as
their system timer by replacing CONFIG_HPET with CONFIG_APIC_TIMER_TSC.
Signed-off-by: Dong Wang <dong.d.wang@intel.com>
adsp_memory.h is pretty much the same for all ace platforms.
Generalize it getting register address from devicetree and
and move it to a common place.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Platforms that support IPIs allow them to be broadcast via the
new arch_sched_broadcast_ipi() routine (replacing arch_sched_ipi()).
Those that also allow IPIs to be directed to specific CPUs may
use arch_sched_directed_ipi() to do so.
As the kernel has the capability to track which CPUs may need an IPI
(see CONFIG_IPI_OPTIMIZE), this commit updates the signalling of
tracked IPIs to use the directed version if supported; otherwise
they continue to use the broadcast version.
Platforms that allow directed IPIs may see a significant reduction
in the number of IPI related ISRs when CONFIG_IPI_OPTIMIZE is
enabled and the number of CPUs increases. These platforms can be
identified by the Kconfig option CONFIG_ARCH_HAS_DIRECTED_IPIS.
Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
headers for dmic are now part of the SoC and maintained per generation,
so create one header for PTL and build the code for PTL in some of the
drivers (dmic_nhlt).
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit adds definition of ACE 3.0 Panther Lake board.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
power_down() expects a cached pointer. Fix the sparse annotation
to match the implementation (sys_cache_cached_ptr_get() returns a cached
pointer so this is correct).
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
This commit introduces support for an alternate linking method in the
LLEXT subsystem, called "SLID" (short for Symbol Link Identifier),
enabled by the CONFIG_LLEXT_EXPORT_BUILTINS_BY_SLID Kconfig option.
SLID-based linking uses a unique identifier (integer) to identify
exported symbols, instead of using the symbol name as done currently.
This approach provides several benefits:
* linking is faster because the comparison operation to determine
whether we found the correct symbol in the export table is now an
integer compare, instead of a string compare
* binary size is reduced as symbol names can be dropped from the binary
* confidentiality is improved as a side-effect, as symbol names are no
longer present in the binary
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
