Commit Graph

63 Commits

Author SHA1 Message Date
Brandon Allen
3176ec55bb soc: esp32s3: bump esp32s3 bootloader iram and dram sizes.
Currently the RAM allocated for the bootloader is not
enough to use MCUBoot with crypto signatures.
This commit bumps the #defines accordingly to fix
compile errors with ecdsa_p256 and RSA.

Signed-off-by: Brandon Allen <brandon.allen@exacttechnology.com>
2024-09-20 11:53:11 -05:00
Marek Matej
a0d7016e27 soc: espressif: Simple boot validity
Update CONFIG_ESP_SIMPLE_BOOT to exclude if CONFIG_MCUBOOT=y
Fix usage of the config according to actual definition.

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2024-09-19 18:02:20 -04:00
Raffael Rostagno
cc6ba10142 soc: espressif: Default MCUboot mode for ESP32 family
Include default MCUboot mode for all ESP32 chips

Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
2024-09-16 20:17:44 +02:00
Sylvio Alves
aa3dd674a9 soc: esp32xx: update flash initialization
Rework how flash is initialized in esp32 SoC.
"esp_flash_app_init()" will make sure proper cache handling
will be set in place.i

Fixes #77551

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2024-09-13 11:36:58 -05:00
Raffael Rostagno
bd3b731ddc soc: esp32c2: esp8684: Console baudrate from device tree
Get console baudrate property from device tree to allow
proper configuration for 26 and 40 Mhz devices.

Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
2024-09-10 17:17:17 -04:00
Sylvio Alves
8233b70ece espressif: clean up unused code
Remove all entries that as not being used.
This also update hal to re-enable warning flags
as such as -Wno-unused-variable.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2024-09-09 13:55:39 -04:00
Marcio Ribeiro
baf62b7a98 soc: esp32: XIP removed from Espressif targets
The way ESP32 XIP works (with MMU and cache) does no fit the way Zephyr XIP
is implemented, causing issues related to included Zephyr linker files.
Flash code still resides in flash for execution, but MMU/Cache handles it
in such way that XIP might not (or should not) be used with current Zephyr
approach. To address this problem, XIP configuration option is being
removed from Espressif targets.

Signed-off-by: Marcio Ribeiro <marcio.ribeiro@espressif.com>
2024-08-31 06:47:52 -04:00
Lucas Tamborrino
5dc545290c soc: espressif: psram as shared multi heap
Currently, if the user wants to allocate heap on external RAM
he needs to enable CONFIG_ESP_SPIRAM and set a threshold defined
with CONFIG_ESP_HEAP_MIN_EXTRAM_THRESHOLD.

This approach requires that we re-implement `k_malloc` and allocate
the memory on the proper region based on the block size.

By using the shared multi heap feature the proccess of allocating
memory from external memory becomes more fluent and simple.

The attribute SMH_REG_ATTR_EXTERNAL was added to reference the
external memory.

Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
2024-08-27 18:37:47 -04:00
Sylvio Alves
b7b03e5682 soc: esp32: kconfig: add unsupported revision config
ESP32 SoC has multiple revisions, some of which are not supported
by the current implementation, as such as REV0 and REV1. This PR
adds an option to indicate user that this is not recommended and not
supported.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2024-08-24 07:15:50 -04:00
Raffael Rostagno
4fc8033d88 soc: mp: esp32: Added IRQ priority and flags config
Interrupt priority and flags config for crosscore ISR
sourced from device tree.

Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
2024-08-22 14:25:25 -04:00
Marcio Ribeiro
f86314ecb6 logging: startup: esp32: startup log messages format unification
Unification of startup log messages format while using SIMPLEBOOT.

Signed-off-by: Marcio Ribeiro <marcio.ribeiro@espressif.com>
2024-08-20 14:53:42 -04:00
Raffael Rostagno
fad55d18ad soc: esp32c2: Add support to ESP32C2 and ESP8684
Files for SoC support: ESP32C2 and ESP8684 (same core).
Basic device tree configuration.

Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
2024-08-16 14:08:22 -04:00
Raffael Rostagno
3ee2a62a55 pm: esp32c6: Power management support
Power management support (light/deep sleep) for ESP32C6

Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
2024-08-15 11:59:08 -04:00
Jamie McCrae
d4a29becf4 soc: espressif: Add default MCUboot mode to sysbuild
Adds the default MCUboot operating mode when building for these
SoCs using sysbuild

Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
2024-08-12 15:14:45 +02:00
Marcio Ribeiro
4bdcf44a8c cleanup: soc: esp32: IDF_TARGET parameters removal
IDF_TARGET parameters removed from soc/Kconfig and landed on Espressif hal

Signed-off-by: Marcio Ribeiro <marcio.ribeiro@espressif.com>
2024-08-11 19:16:04 -05:00
Marek Matej
795ac34f29 soc: espressif: Use WiFi config file
Add config file to host WiFi specific settings.
Introduce CONFIG_ESP_WIFI_MAX_THREAD_PRIO to be used
as a cap for the LL driver runtime.

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2024-08-09 09:54:36 +02:00
Anas Nashif
dbfbf0edba xtensa: adapt soc code to use prep_c
Many xtensa target jump from soc code directly into cstart and depend on
architecture code being initialized in arch_kernel_init(). Instead of
jumping to cstart, jump to newly introduced prep_c similar to all other
architectures, where common platfotm initialization will happen.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2024-08-07 13:50:53 +02:00
Felipe Neves
af91d06b00 drivers: mbox: mbox_esp32: add support for esp32 MBOX driver
as an alternative for IPM driver.

Signed-off-by: Felipe Neves <ryukokki.felipe@gmail.com>
2024-08-07 07:17:01 -04:00
Sylvio Alves
c374d3147b linker: esp32: fix cpp rom region
cplusplus-rom linker initialization was wrongly placed
in RAM area when it should be in ROM area.

Fixes #75853

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2024-08-06 17:17:24 -04:00
Gero Schwäricke
776ecbca0f soc: espressif: esp32: add WROVER-E-N16R4 SiP variant
It seems this SiP variant is not sold by espressif directly, but it is
used by the Odroid Go. The Odroid Go documentation calls this a "custom"
model [1].

There already exists a SiP specific device tree include file:

  zephyr/dts/xtensa/espressif/esp32/esp32_wrover_e_n16r4.dtsi

[1] https://wiki.odroid.com/odroid_go/odroid_go#specifications

Signed-off-by: Gero Schwäricke <gero.schwaericke@posteo.de>
2024-08-02 03:30:25 -04:00
Alberto Escolar Piedras
c346c77a2a soc/espressif/esp32c6: Do not set HAS_PM or HAS_POWEROFF
The source files required for this features are not present
in the tree for this SOC.
So if CONFIG_PM or CONFIG_POWEROFF are enabled, there would
be a cmake failure.

Let's just indicate these features are not supported in
kconfig.

Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
2024-07-16 12:53:09 -04:00
Sylvio Alves
0c5d5f796f soc: espressif: disable RNG entropy before app runs
SARADC was kept enabled to feed RNG entropy peripheral,
adding instability to Wi-Fi connection. So we disable it
before app runs as RNG driver already got initial entropy values.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2024-07-11 16:19:55 -04:00
Sylvio Alves
3163680427 soc: esp32c6: remove idle source file
risc-v idle call is being fetched from arch/ implementation.
This soc file is not used and can be removed.

Fixes #75540

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2024-07-08 12:12:21 -04:00
Sylvio Alves
f65770c1a1 soc: esp32xx: always use section prologue with alignment
ESP32 requires proper alignment between sections. There are some
scenarios, as reported in #74533, that the section can
get shifted, causing runtime failure.
Making sure SECTION_PROLOGUE is used with ALIGN_WITH_INPUT
will guarantee its consistency.

Fixes #74533

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2024-06-28 21:00:11 -04:00
Marek Matej
6a7c8d789f soc: espressif: Update MCUboot segment size
- Fix the build issues with the insufficient memory for
  the MCUboot.
- Fix the sysbuild with MCUboot tests on all ESP32xx SoCs.

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2024-06-26 09:01:25 -04:00
Alberto Escolar Piedras
6e977ae2d5 lib c/cpp: Move .ctor .init_array handling from C++ to kernel
* Move ctors and init_array from the CPP library
  to the kernel library, as this is common for both C
  and C++ and it is the kernel who is running it.
* Rename the hidden kconfig option CPP_STATIC_INIT_GNU
  STATIC_INIT_GNU instead.
* If STATIC_INIT_GNU is not selected verify there is
  constructors left behind.
* Rename common-rom-cpp.ld to common-rom-init.ld
* Rename z_cpp_init_static to z_init_static,
  and have the kernel always call it.

Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Signed-off-by: Keith Packard <keithp@keithp.com>
2024-06-25 19:14:37 -04:00
Romain Pelletant
8e6cff0176 soc: esp32: fix unknown defined for linker
* Fix unknown define at link stage when CONFIG_BT is enabled
Solve #74836

Signed-off-by: Romain Pelletant <romain.pelletant@fullfreqs.com>
2024-06-24 14:25:37 +02:00
Sylvio Alves
ee1b13c822 soc: esp32c3: fix tls linking error
Fix linking error due undefined tdata entry.
After #72642, tdata could be undefined due to
missing TLS check.

Fixed #74852

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2024-06-24 14:25:18 +02:00
Sylvio Alves
b38d4300b9 soc: esp32c3: fix TLS flash addressing
When TLS is used, `__tdata_start` is PROVIDED by
"thread-local-storage.ld" using absolute address, which
makes it land in wrong flash address. This causes risc-v startup
code to fail during memcpy/memset.

This PR overrides `__tdata_start` to use ADDR, which will
make sure it is placed in DROM region due to AT keyword.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2024-06-20 14:07:54 -04:00
Marek Matej
e5de9d2447 soc: espressif: esp32: improve memory utilization
Move the user_iram_end boundary to allow more statical allocations.

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2024-06-19 13:23:47 -04:00
Marek Matej
90ecdf0dab soc: espressif: esp32s2: improve memory layout
- Allow more statical allocations by reordering the sections
  in the mcuboot.ld and in default.ld.
- Reorder the ROM sections to cover the cases described in
  the `common-rom-common-kernel-devices.ld`.
  Changing the order of .rodata and .text we prevents to create an
  overlapped segments issue.

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2024-06-15 05:19:00 -04:00
Raffael Rostagno
9265c82313 soc: esp32c6: Kconfig and .ld updates, DTS and comments fix
Kconfig, .ld and comments fixing
Fixed address of UART1, WDT and RTC timer disabled by default

Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
2024-06-14 18:51:46 -04:00
Raffael Rostagno
6096a10b9a drivers: clock_control: Refactor for ESP32C6
Added support for C6 to allow CPU clock config

Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
2024-06-14 18:51:46 -04:00
Raffael Rostagno
67e43f6a81 drivers: intc: Fix for ESP32C6 interrupt sources allocation
Fix to properly allocate IRQs for interrupt sources over 60.
It also screens out non-allocatable IRQs used by the CPU.

Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
2024-06-14 18:51:46 -04:00
Marek Matej
b3523c9bfa soc: espressif: add esp32-c6 support
Add basic support for esp32c6 SoC.

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2024-06-14 18:51:46 -04:00
Marek Matej
51e5f2d3e5 soc: espressif: esp32c3: reorder ROM sections
This covers the cases described in common-rom-common-kernel-devices.ld
Changing the order of .rodata and .text we prevents to create an
overlapped segments issue.

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2024-06-13 16:47:05 -04:00
Marek Matej
7bf47f8e8f soc: espressif: esp32c3: improve memory utilization
Change the MCUboot segments layout to incread the memory
available in the application.
Add missing symbols to mcuboot.ld

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2024-06-13 16:47:05 -04:00
Marek Matej
9f1a4e3e4f soc: espressif: esp32s3: add cross segment call check
Add build check that would detect unwanted calls
from the `iram0.loader_text`, which is the last
bootloader segment to be alive.

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2024-06-10 16:58:28 +03:00
Marek Matej
61bb79c7ea soc: espressif: esp32s3: fix memory utilization
Fixed bootloader memory layout.
Improved memory utilization.

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2024-06-10 16:58:28 +03:00
Peter Mitsis
0bcdae2c62 kernel: Add CONFIG_ARCH_HAS_DIRECTED_IPIS
Platforms that support IPIs allow them to be broadcast via the
new arch_sched_broadcast_ipi() routine (replacing arch_sched_ipi()).
Those that also allow IPIs to be directed to specific CPUs may
use arch_sched_directed_ipi() to do so.

As the kernel has the capability to track which CPUs may need an IPI
(see CONFIG_IPI_OPTIMIZE), this commit updates the signalling of
tracked IPIs to use the directed version if supported; otherwise
they continue to use the broadcast version.

Platforms that allow directed IPIs may see a significant reduction
in the number of IPI related ISRs when CONFIG_IPI_OPTIMIZE is
enabled and the number of CPUs increases.  These platforms can be
identified by the Kconfig option CONFIG_ARCH_HAS_DIRECTED_IPIS.

Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
2024-06-04 22:35:54 -04:00
Mathieu Choplain
8aa6ae43ce llext: add support for SLID-based linking
This commit introduces support for an alternate linking method in the
LLEXT subsystem, called "SLID" (short for Symbol Link Identifier),
enabled by the CONFIG_LLEXT_EXPORT_BUILTINS_BY_SLID Kconfig option.

SLID-based linking uses a unique identifier (integer) to identify
exported symbols, instead of using the symbol name as done currently.
This approach provides several benefits:
 * linking is faster because the comparison operation to determine
   whether we found the correct symbol in the export table is now an
   integer compare, instead of a string compare
 * binary size is reduced as symbol names can be dropped from the binary
 * confidentiality is improved as a side-effect, as symbol names are no
   longer present in the binary

Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
2024-06-03 15:29:34 -04:00
Yong Cong Sin
bbe5e1e6eb build: namespace the generated headers with zephyr/
Namespaced the generated headers with `zephyr` to prevent
potential conflict with other headers.

Introduce a temporary Kconfig `LEGACY_GENERATED_INCLUDE_PATH`
that is enabled by default. This allows the developers to
continue the use of the old include paths for the time being
until it is deprecated and eventually removed. The Kconfig will
generate a build-time warning message, similar to the
`CONFIG_TIMER_RANDOM_GENERATOR`.

Updated the includes path of in-tree sources accordingly.

Most of the changes here are scripted, check the PR for more
info.

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
2024-05-28 22:03:55 +02:00
Lucas Tamborrino
e282b0ea84 soc: esp32xx: refactor clock and RTC subsystems
The RTC subsystem in espressif's SOCs, among other tasks
is responsible for clock selection for CPU and for low
power domain clocks such as RTC_SLOW and RTC_FAST.

This commit allows for proper clock source and rate
selection for CPU, using the espressif,riscv and
espressif,xtensa-lx6/7 bindings.

It also enables clock selection for RTC_FAST and RTC_SLOW,
that impacts some peripherals, such as rtc_timer.

Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
2024-05-27 01:37:18 -07:00
Sylvio Alves
3f07d4b6ab soc: espressif: add misssing external xtal kconfig entry
External XTAL usage is missing a Bootstrap Cycle configuration
in Kconfig, causing build to failure when CONFIG_RTC_CLK_SRC_EXT_CRYS
is selected.

Fixes #72190

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2024-05-07 21:21:46 -04:00
Marek Matej
8c373b9bae soc: espressif: Fix the cache size set calls
Move the cache size set calls from soc.c do common loader.c
for all related SOCs. Remove unnecessary includes.

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2024-04-19 10:07:15 +02:00
Sylvio Alves
9153f70da1 soc: esp32: spiram: add ECC config
Adds ECC feature to be enabled for esp32s3 SoC.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2024-04-18 08:05:22 -07:00
Marek Matej
213bad1de0 soc: espressif: add missing linker symbols
Provide missing symbols to the default linker scripts.

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2024-04-15 16:26:20 +02:00
Marek Matej
2395f08d48 soc: espressif: esp32: simple boot support
Add simplistic booting method which allows to run
applications without the 2nd stage bootloader.

- introduce memory layout header file
- update and optimize default and mcuboot linker scripts
- remove building multiple binaries during the application build

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2024-04-08 09:16:41 -04:00
Marek Matej
323f811c7c soc: espressif: esp32s2: simple boot support
Add simplistic booting method which allows to run
applications without the 2nd stage bootloader.

- introduce memory layout header file
- update and optimize default and mcuboot linker scripts
- remove building multiple binaries during the application build

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2024-04-08 09:16:41 -04:00
Marek Matej
553238704f soc: espressif: esp32s3: simple boot support
Add simplistic booting method which allows to run
applications without the 2nd stage bootloader.

- introduce memory layout header file
- update and optimize default and mcuboot linker scripts
- remove building multiple binaries during the application build

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2024-04-08 09:16:41 -04:00