Add MCO device nodes to the STM32 boards.
The set of supported boards are chosen to replace what is currently
supported in Kconfig.
Signed-off-by: Joakim Andersson <joerchan@gmail.com>
Add clock sources that can be output by the MCO on the stm32f1x and
stm32f10 connectivity line devices.
Signed-off-by: Joakim Andersson <joerchan@gmail.com>
Adds Device Tree include files for all MCUs in the STM32WB0 series.
These DTSI files only contain the supported peripherals for now.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
we have four i2C peripherals .
- three shared between stm32u031/73/83
- One between stm32u073/83
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
The STM32 SPI driver, `spi_ll_stm32.c`, reads the clock frequency via
`clock_control_get_rate()`. The first `clocks` index is used as subsystem
argument if there is no second index, but this is not the source clock for
SPI 1, 2, and 3.
This causes the prescaler value calculation to be incorrect, resulting in a
frequency potentially above the `spi-max-frequency` value.
Add clock source for SPI instances 1, 2 and 3, that matches the default
clock configuration register reset value, which resolves the issue.
Signed-off-by: Jeppe Odgaard <jeppe.odgaard@prevas.dk>
since stm32h7.dtsi is already include in st/h7/stm32h743.dtsi
we don't need to include here again.
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
The flash controller is nowadays supported on the M4 core.
Add the bank2-flash-size property to the board definitions as required
by the STM32 H7 flash driver.
Signed-off-by: Tomi Fontanilles <tomi.fontanilles@nordicsemi.no>
For almost all STM32 GPIO controllers, the number of supported GPIO
pins managed by a single controller is 16 (with some exceptions for
fewer). However, the default for ngpios in the device tree bindings
for gpio-controllers is 32; leading to inaccuracies in handling GPIO
for these controllers, such as presenting too many GPIOs in the GPIO
shell. This patch redefines the default for ngpios for "st,stm32-gpio"
compatible devices to 16 and adds the correct ngpios for the few
exceptions Zephyr current supports.
Signed-off-by: Michael R Rosen <mrrosen@alumni.cmu.edu>
This commit moves the backup sram definition to the
series base dtsi file, the size is overwritten for socs
which have a bigger bkpsram.
The backup SRAM is available on all stm32h5 mcus.
stm32h503/523/533 have 2k
stm32h562/563/573 have 4k
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
since h750 and h743 have the same irq wkup priority,
we can add wkup interrupt in h743.dsti and simply
include the file in h750.dtsi.
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
Since the clock node is not a child node of the soc node,
but from the root node.
This removes the warning log at compilation.
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
add reset control registers information (on RCC_BUS_RSTR LTDCRST bit)
for display peripheral reset.
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
Add support for the stm32h755 which is a close relative of
the stm32h745 with additional cryptography and hashing
peripherals.
Signed-off-by: Mike Banducci <michael.banducci@sandc.com>
This commit add the description of the fmc in the SoC stm32l5, and the
description of the screen controller st7789v in the board stm32l562e-dk.
Signed-off-by: Miguel Gazquez <miguel.gazquez@bootlin.com>
LPTIM is not available in STOP3 mode, so RTC needs to be used instead.
This code usese similar approach as STM32WBAx for suspend to ram.
The STOP3 is disabled by default in device tree.
Signed-off-by: Adam Berlinger <adam.berlinger@st.com>
Add the IWDG and WWDG watchdog peripherals
the ADC1 & 2 peripherals with sensor for die temperature and voltage
the RNG entropy generator
Signed-off-by: Francois Ramu <francois.ramu@st.com>
I also added an overlay file for the nucleo_h563zi board to the
samples/boards/stm32/backup_sram example.
Signed-off-by: Thorsten Spätling <thorsten.spaetling@vierling.de>
Convert the hci_stm32wba.c driver to the new HCI API. Unlike in most cases,
the devicetree node is already enabled on the SoC level (rather than board
level). This is in order to mirror how the Kconfig option was originally
enabled, i.e. on the SoC level.
Signed-off-by: Johan Hedberg <johan.hedberg@gmail.com>
On STM32G0, the backup memory is defined as part of the TAMP peripheral.
Use the same workaround as on STM32WL to add the node as part of the
RTC.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Add the new stm32h7rs serie with stm32H7R3, stm32H7R7,
stm32H7S3, stm32H7S7 devices from STMicroelectronics
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add devicetree node of stm32 PWR peripheral that controlls wake-up pins.
The new node includes child nodes for wake-up pins configuration.
We only add these nodes for STM32 SoC series that support Poweroff.
Signed-off-by: Abderrahmane Jarmouni <abderrahmane.jarmouni-ext@st.com>
Add a digi_dietemp node for the STM32 Digital Temperature Sensor into
stm32h723.dtsi (used as a base for H723, H725, H730 and H735) and
stm32h7a3.dtsi (used as a base for H7A3, H7B0 and H7B3).
The sensor is not available on other H7 SoCs.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Align interrupt numbering with RM0436 for STM32MP157.
This will allow EXTI interrupt for line 6, 7, 8, 9, 10 and 11.
Fixes: ff231fa20a ("dts: stm32: Populate new properties for exti nodes")
Signed-off-by: Sean Nyekjaer <sean@geanix.com>
By default, the QSPI region is marked as EXTMEM and inaccessible
(see #57467), mark the first 64MB as IO on stm32f769i_disco.
Signed-off-by: Armin Brauns <armin.brauns@embedded-solutions.at>
Define the xspi node instead of ospi. Note that RCC CCIPR4 register
keeps the OCTOSP1 for clock domain selection.
Change the header file to xspi for the stm32 devices with xspi
peripheral. Keep the flash_controller/ospi.h for bindings compatibilty.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add mdio node for h5 and h7 series.
Since MDIO registers are part of the same ETH hw IP, keeping mdio
node just as a child of mac/eth, cannot see as appropriate to assign
an adddress to it.
Signed-off-by: Angelo Dureghello <adureghello@baylibre.com>
Set RNG address to its non-secure alias.
See RM0493 STM32WBA5 Reference manual for details.
Using the secure alias (0x5..)instead of the non-secure alias (0x4..)
for this peripheral results in a SecureFault during kernel init if
TrustZone is activated, Zephyr is running as NSPE and RNG is
enabled.
Signed-off-by: Louis Feller <louis.feller@st.com>
