Introduce GPIO-based driver for MIPI DBI class that allows MIPI DBI
type A and B displays to be used on general platforms.
Since each data pin GPIO can be selected individually, the bus pins are
set in a loop, which has a significant negative impact on performance.
When using 8-bit mode and all the data GPIO pins are on the same port,
a look-up table is generated to set the whole port at once as a
performance optimization. This creates a ROM overhead of about 1 kiB.
Tested 8-bit 8080 mode with ILI9486 display on nRF52840-DK board.
Signed-off-by: Stefan Gloor <code@stefan-gloor.ch>
HFXO is represented as a child of the oscillators node. A new node is
created because it requires its own properties (see the binding for more
details).
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
LFXO is represented as a child of the oscillators node. A new node is
created because it requires its own properties (see the binding for more
details).
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
- Create a new compatible: nordic,nrf53x-oscillators, as other series,
e.g. nRF54LX contain a similar but different IP (with PLL control,
etc.)
- Adjust DT: use recommended node name, remove redundant status okay.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Register all the lpi2c instances.
Add no-power-level property and update driver
to adapt no-power-level property.
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
This defines raspberrypi,pico-xosc along with a configurable startup
delay multiplier. On some boards, the XOSC takes longer to stabilize.
Signed-off-by: Xudong Zheng <7pkvm5aw@slicealias.com>
This fixes the following warning:
> unit address and first address in 'reg' (0x1002c0) don't match for
> /soc/dma@100200
Signed-off-by: Reto Schneider <reto.schneider@husqvarnagroup.com>
This fixes the following warning:
> unit address and first address in 'reg' (0x3fc70) don't match for
> /soc/peripheral@40000000/flash-controller@34000/flash@9fc70
Signed-off-by: Reto Schneider <reto.schneider@husqvarnagroup.com>
This fixes the following warnings:
> unit address and first address in 'reg' (0x40094000) don't match for
> /soc/peripheral@40000000/usbhs@144000
Signed-off-by: Reto Schneider <reto.schneider@husqvarnagroup.com>
This fixes the following warning:
> unit address and first address in 'reg' (0x3fc70) don't match for
> /soc/peripheral@40000000/flash-controller@34000/flash@9fc70
Signed-off-by: Reto Schneider <reto.schneider@husqvarnagroup.com>
This fixes the following warnings:
> unit address and first address in 'reg' (0x40094000) don't match for
> /soc/peripheral@40000000/usbhs@144000
Signed-off-by: Reto Schneider <reto.schneider@husqvarnagroup.com>
Now that we support internally connected channels we should make the
pinctrl configuration optional.
Signed-off-by: Corey Wharton <xodus7@cwharton.com>
Add MCO device nodes to the STM32 boards.
The set of supported boards are chosen to replace what is currently
supported in Kconfig.
Signed-off-by: Joakim Andersson <joerchan@gmail.com>
Add clock sources that can be output by the MCO on the stm32f1x and
stm32f10 connectivity line devices.
Signed-off-by: Joakim Andersson <joerchan@gmail.com>
Add board support for eval board ganymed_bob, which
is a break-out-board for both soc variants.
Variants of the soc are GBM and GEN1.
Signed-off-by: Sven Ginka <s.ginka@sensry.de>
Indicate in the STM32WB0 power controller binding that the SMPS output
current limitation is a feature only available on STM32WB05 and STM32WB09.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
`-` is preferred over `_` in devicetree property names.
Since, change `clk_src`, `clk_div`, and `clk_out_div` to
`clk-src`, `clk-div`, and `clk-out-div`.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
There is an issue on the SHI hardware peripheral to detect CS
rising/failing with bits CSnFE/CSnRE in the EVSTAT2 register in
npcx9m7fb chip. This commit workarounds it by using MIWU to detect the
CS rising and failing.
Signed-off-by: Tom Chang <CHChang19@nuvoton.com>
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
The internal flash size of npcx9m7fb is 512KB. Reduce the default
Code RAM size from 320KB to 256KB because the Code RAM size is limited
by FLASH_SIZE/2 in the Chromebook EC application.
Signed-off-by: Tom Chang <CHChang19@nuvoton.com>
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Add common default flash partition layout for nrf52840 as many boards
have used identical flash layouts.
The default flash layout was updated to remove scrach in 2022 (9a84258)
but almost all boards were still using the previous layout, so this
updates them to the new layout with allows for larger applications.
This commit also incorporates feeedback from @nordicjm in PR #77791 to
change slot0 to 0x00077000 and slot1 to 0x00075000: "If you use swap
using move, you need a sector for the data to be moved up by, and you
need space for the swap status fields, which is about a sector, so by
making the changes here you get the full 0x65000 for an image, without
these changes you get 0x64000.
Signed-off-by: Jacob Winther <jacob@9.nz>
Adds Device Tree include files for all MCUs in the STM32WB0 series.
These DTSI files only contain the supported peripherals for now.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
