Removed single offset alignment check mechanism and replaced it with
offset alignment check for each iteration
Signed-off-by: Madhurima Paruchuri <mparuchuri@google.com>
The spi_nor erase op selection was based on the alignment of the end of
the region to be erased. This prevented larger erase operations being
selected in many cases
Closes#60904
Signed-off-by: Joshua Crawford <joshua.crawford@levno.com>
Modify the NPCX driver erase method to allow 0x1000 byte size erases
along with 0x10000 byte size erases based on input parameters
Signed-off-by: Madhurima Paruchuri <mparuchuri@google.com>
Most implementations have the same logic, with only a different write
block size. Now that we are using write-block-size from the device tree,
it is possible to use a default implementation that can be overridden if
necessary.
Signed-off-by: Florian Vaussard <florian.vaussard@gmail.com>
STM32L5 have a write block size of 8, but STM32U5 and STM32H5 have a
write block size of 16. Convert write_dword() and
flash_stm32_write_range() to write write-block-size data at a time.
Fixes#60724
Signed-off-by: Florian Vaussard <florian.vaussard@gmail.com>
STM32L5 have a write block size of 8, but STM32U5 and STM32H5 have a
write block size of 16. Use write-block-size from the device tree
instead of hardcoding this value when validating the range of write
operations.
Fixes#60724
Signed-off-by: Florian Vaussard <florian.vaussard@gmail.com>
Add support for flash NOR memory devices on a NXP S32 QSPI bus. The
driver uses a fixed LUT configuration assuming a default standard page
size and erase types, and allows to select between multiple read/program
instructions/modes. It is also possible to read the flash device
characteristics from the device at run-time as long as the memory is
JESD216 compatible, providing more flexibility.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Refactor the ESP32 target SOCs together with
all related boards. Most braking changes includes:
- changing the CONFIG_SOC_ESP32* to refer to
the actual soc line (esp32,esp32s2,esp32s3,esp32c3)
- replacing CONFIG_SOC with the CONFIG_SOC_SERIES
- creating CONFIG_SOC_FAMILY_ESP32 to embrace all
the ESP32 across all used architectures
- introducing CONFIG_SOC_PART_NUMBER_* to
provide a SOC model config
- introducing the 'common' folder to hide all
commonly used configs and files.
- updating west.yml to reflect previous changes in hal
Signed-off-by: Marek Matej <marek.matej@espressif.com>
Add Nuvoton numaker series flash memory controller(FMC) with erase,
read & write features of soc-flash. Also update Nuvoton manifest
to include zephyrproject-rtos/hal_nuvoton#6.
Signed-off-by: cyliang tw <cyliang@nuvoton.com>
This CL attempts to implement npcx's flash driver instead of the
original one (npcx spi driver plus spi_nor flash driver).
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Flash API states that drivers should support write requests without
any restrictions on location or alignment of the source buffer.
Due to hardware limitations of the QSPI peripheral, the nrf_qspi_nor
driver currently fails to perform a write from a RAM buffer that is
not word-aligned. Fix this by using in such case the same mechanism
that is used when the source buffer is located in the internal flash
(copy data to a buffer located on stack).
Also correct the length parameter for writes from this stack-based
buffer to be the actual data chunk length, not always the size of
the buffer (as for CONFIG_NORDIC_QSPI_NOR_STACK_WRITE_BUFFER_SIZE > 4
this may lead to overwriting of some data located next in the flash).
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Refactor the part of the flash simulator that interacts with the
host when build for native platforms, so it is possible to use
it also with the embedded libCs.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Support device power management in spi_nor driver. Only use
SUSPEND/RESUME if `CONFIG_SPI_NOR_IDLE_IN_DPD` is not enabled to avoid
state conflicts.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
This commit adds the jedec216 read sfdp and Read ID
function API. The qspi commands are issued to the
quad flash device.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Avoid timeout when taking semaphores in ISR.
This enables flash operations inside interrupted context
such as exceptions, allowing operations like saving core
dump to flash for instance.
Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
Allows to configure OSPI Manager IO ports with devicetree.
If properties are absent, then original default values
are preserved for compatibility.
Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
This adds a few line use zephyr_syscall_header() to include
headers containing syscall function prototypes.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Copy the LUT to SRAM before updating it. This avoids the application
reading LUT entries from FlexSPI while trying to write them to FlexSPI
configuration registers, which could result in invalid LUT entries being
added.
This update is applied to all in tree flash FlexSPI drivers, although
the failure has only been observed with the flash_mcux_flexspi_nor
driver.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This make MCUboot build as Zephyr application.
Providing optinal 2nd stage bootloader to the
IDF bootloader, which is used by default.
This provides more flexibility when building
and loading multiple images and aims to
brings better DX to users by using the sysbuild.
MCUboot and applications has now separate
linker scripts.
Signed-off-by: Marek Matej <marek.matej@espressif.com>
Like other stm32 drivers, especially the stm32 flash ospi,
the DMA callback accepts a null or positive status.
It returns an error in case of negative.
BTW it also sets variable as unused, like stm32 flash ospi does.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Replace memcpy usage in write since it is not linked to non-external
flash which might cause read-while-write issues.
Move the function that invalidated the data cache inside the critical
section to avoid context switch before it is invalidated.
Signed-off-by: Jeppe Odgaard <jeppe.odgaard@prevas.dk>
Check memc_flexspi_is_running_xip before calling
memc_flexspi_set_device_config in hyperflash init.
This aligns with the nor flash driver.
Signed-off-by: Jeppe Odgaard <jeppe.odgaard@prevas.dk>
Hyperflash write operations resulted in invalid writes. This commit
fixes the issue by temporarily lowering the clock during writes.
This aligns with the mcux-sdk-examples.
Fixes https://github.com/zephyrproject-rtos/zephyr/issues/53855
Signed-off-by: Jeppe Odgaard <jeppe.odgaard@prevas.dk>
Add a function to wait for the full (bulk) Nor-octoflah erase command.
When erasing the full octo-flash, the drivers waits until
the operation is ready and the external NOR mem becomes ready itself.
The full (bulk) erase operation lasts for several seconds.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
- Update KCONFIG for flash driver to depend on
DT_HAS_FIXED_PARTITIONS_ENABLED, since that is necessary for the
driver implementation
Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
Most available AT45 flash chips have their first two sectors shorter
than the consecutive ones. Usually, the first sector is marked as 0a
and has its size equal to eight pages (one block) and the second one
(usually 0b) is the complement to the size of a regular sector.
This commits modifies the driver so that erasing of these first two
sectors is performed correctly. This modified behavior is configurable
with a new DT property so that it is still possible to also use legacy
AT45 chips that do not feature such sector split. Such legacy chips
usually also do not support the chip erase and sector erase commands,
so two more DT properties are introduced to cover that.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
- Added initial version of Infineon CAT1 Flash driver
- Added binding file for infineon,cat1-flash-controller.yaml
- Added overlays for subsys/nvs and drivers/flash_shell
to support cy8cproto_063_ble, cy8cproto_062_4343w boards
- Defined erase-block-size in PSoC6 MPN dtsi.
Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
Use new nrfx hal function to memcpy from flash
instead of accessing the array directly.
That function is inlining a memcpy for real targets,
so there is no practical difference for those.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Make use of positive status values in the DMA callback to pass
info to the DMA client after a successful DMA operation.
A completed DMA transfer uses the status 0 while a reached
water mark uses the status 1.
Signed-off-by: Cyril Fougeray <cyril.fougeray@worldcoin.org>
Add the ability for the flash simulator to store its contents in a
memory region.
This allows filesystems on the flash simulator to survive a reboot.
And allows subsystems (e.g. coredump) to store their info on ram while
using the (existing) flash partition backend.
Add a example (for nucleo_f411re) that shows how to configure the flash
simulator for hardware (cfg discussion #54166).
Signed-off-by: Laczen JMS <laczenjms@gmail.com>
This fixes this bug:
https://github.com/zephyrproject-rtos/zephyr/issues/57498
If bit 1 is set, then a write enable is required before
sending the 0xb7 instruction to enable the 4 byte address
mode, which this PR implements.
Signed-off-by: Frank Buss <fb@frank-buss.de>
SPI / QSPI flash with density above 16MB must use 4 byte addressing mode
also on sector erase.
This patch selects the right addressing mode and opcode when 4 byte
addressing mode is selected
Signed-off-by: Brian Juel Folkmann <bju@trackunit.com>
Mark the device as busy when it is locked to perform a flash operation
so that the PM subsystem does not try to suspend it. Also refuse to run
a PM action when the device is busy (in case `qspi_nor_pm_action()` is
called directly, not by the PM subsystem).
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Original computation seems to be based on
QSPI that has prescaler range [0, 255].
However, OSPI clock prescaler has different
value range [1, 256].
Adapt prescaler computation to valid OSPI
domain and add min value assert.
Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
For the POSIX architecture, add options to:
* Clear the flash content at boot
* To delete the file on exit
* To just keep the flash in RAM instead of a file in disk
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
The delayblock is bypassed when the <dlyb-bypass> property is true.
DT_NODE_HAS_PROP tests whether the property is defined at all,
not whether a boolean property is true or false.
To get a boolean property’s truth value,
use DT_PROP(node_id, prop) instead.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Remove all init functions that do nothing, and provide a `NULL` to
*DEVICE*DEFINE* macros.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Normally, the driver deactivates the QSPI peripheral for periods when
no QSPI operation is performed. This is done to avoid increased current
consumption when the peripheral is idle. For the same reason, the base
clock on nRF53 Series SoCs (HFCLK192M) is configured for those periods
with the default /4 divider that cannot be used otherwise. However,
when XIP accesses are used, the driver must be prevented from doing
both these things as that would make XIP to fail. Hence, a function
is provided so that applications can inform the driver that XIP is
needed and the above idle actions should be suppressed.
This function (`nrf_qspi_nor_xip_enable()`) replaces the old one
(`nrf_qspi_nor_base_clock_div_force()`) that was intended for similar
purpose but after deactivation of the peripheral was introduced in
commit 95d867e8ed it became useless.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
MISRA Rule 5.7 requires uniqueness of tag identifiers. Shell is
frequently problematic because many code uses `const struct shell
*shell`. This causes CI noise every time one of these shell files is
edited, so let's update all of them with `const struct shell *sh`
instead.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
With the stm32h5x, hal driver is xspi for octospi
Add a header file to map functions and constants.
The ospi driver of the stm32H5x serie does not support DMA yet.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Introduce flash extended operations that can be used to disable access
to option and control registers until reset. Disabling access to these
registers improves system security, because flash content (or protection
settings) can't be changed even when exploit was found.
On STM32 devices, registers can be locked until reset by writing wrong
key during unlock procedure. It triggers a bus fault, so during the
procedure we need to ignore faults and clear bus fault pending bit.
Please note that option register disabling was implemented for devices
that have OPTCR register (F2, F4, F7 and H7). Implementation on other
devices requires more testing, since documentation is not precise
enough. Disabling control register was implemented for devices that
have CR register.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
This patch makes possible to choose custom byte which should be used
to enable non-permanent readout protection (RDP1). Actually, any byte
except 0xAA and 0xCC (which are used by RDP0 and RDP2 respectively)
can be used to enable RDP1 but in multi-image environment, some other
image could check if RDP1 is enabled by comparing it to some hardcoded
value.
If property is not defined, 0x55 will be used to enable RDP1. The
default value comes from STM32 HAL.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
This patch adds flash readout protection support for STM32F4 devices
family. These devices can enable protection on entire flash content.
Readout protection functionality was exposed as vendor extended
operation. To change readout protection state, caller should provide a
structure which describes desired RDP state.
Enabling readout protection permanently or disabling readout protection
(changing from level 1 to level 0) is guarded by
CONFIG_FLASH_STM32_READOUT_PROTECTION_PERMANENT_ALLOW and
CONFIG_FLASH_STM32_READOUT_PROTECTION_DISABLE_ALLOW respectively.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
This patch adds sector write protection support for STM32F4 devices
family. These devices can protect flash content with sector precision.
Write protection functionality was exposed as vendor extended operation.
To change write protection state, caller should provide mask of enabled
and disabled sectors.
Function responsible for locking/unlocking option bytes was implemented
for all STM32 devices supported by this driver.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Introduce the stm32h5 serie to the the existing flash driver
It is based on the stm32l5 model.
Add a function to check if the flash is in dual
or single bank mode.
Some stm32 devices can map 2 or 1 flash banks.
Adapt the FLASH register names for the stm32h5 mcu.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Unify the drivers/*/Kconfig menuconfig title strings to the format
"<class> [(acronym)] [bus] drivers".
Including both the full name of the driver class and an acronym makes
menuconfig more user friendly as some of the acronyms are less well-known
than others. It also improves Kconfig search, both via menuconfig and via
the generated Kconfig documentation.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Move the SoC Flash nRF sync ticker implementation into
Bluetooth Controller Subsystem folder, as internal headers
are included.
Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
Add PM_DEVICE_RUNTIME support to nordic QSPI NOR flash driver, putting
the QSPI peripheral and flash ship into DPD if available
Signed-off-by: Zack Cornelius <zcornelius@securityesys.com>
Besides of standard flash operations like write or erase, flash
controllers also support additional features like write protection or
readout protection. These features are not available in every flash
controller, what's more controllers can implement it in a different way.
It doesn't make sense to add a separate flash API function for every
flash controller feature, because it could be unique (supported on small
number of flash controllers) or the API won't be able to represent the
same feature on every flash controller.
Extended operation interface provides flexible way for supporting flash
controller features. Code space is divided equally into Zephyr codes
(MSb == 0) and vendor codes (MSb == 1). This way we can easily add
extended operations to the drivers without cluttering the API or
problems with API incompatibility. Extended operation can be promoted
from vendor codes to Zephyr codes if the feature is available in most
flash controllers and can be represented in the same way.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Since PINCTRL and pinctrl-0 is now required, there's no point in doing
extra validation at driver level. Modify the macro to just check that
sleep state is present when needed, since it was the only remaining
assertion that was not covered. Renamed the macro to make it more clear
what it does: NRF_DT_CHECK_NODE_HAS_PINCTRL_SLEEP
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Move to using 'select SPI' instead of 'depends on SPI'
(see commit df81fef for more details)
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
No need to read back the CR (NOR flash config or control register)
to check if entering the 4-Byte Address Mode is effective.
The action of this command is immediate and the result
(bit field of the CR) is NOR flash vendor-specific.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The check_arr used the TEST_ARR_SIZE value for the size, but
has been removed and replaced with CONFIG_FLASH_SHELL_BUFFER_SIZE.
Signed-off-by: Emil Gydesen <emil.gydesen@nordicsemi.no>
Fixes spi_nor_erase to return -EINVAL instead of -ENODEV
when erase requested is out of flash range.
This makes the SPI NOR return the same error as all other errors.
Fixes#54897
Signed-off-by: Dominik Ermel <dominik.ermel@nordicsemi.no>
Previously when the repeat argument wasn't supplied to the shell
command it would falsely seem to succeed, even though the
test was never run. Instead of displaying an error message this
rather overrides the repeat to 1, so that the test is run once.
Signed-off-by: Hein Wessels <heinwessels93@gmail.com>
Previously cmd_test could falsely give the indication that the
flash driver is functioning properly, because the written data
isn't validated and could have silently failed.
This commit adds a verify step to ensure the data was written successfully.
Signed-off-by: Hein Wessels <heinwessels93@gmail.com>
Requesting page layout triggers filling bank array
only once, and returns pre-filled array on consequential calls.
But ignores array size.
Remember size of this array as well.
Fixes#54563
Signed-off-by: Maciej Zagrabski <mzi@trackunit.com>
spi_nor_sfdp_read is now called from spi_nor_process_sfdp for the
CONFIG_SPI_NOR_SFDP_RUNTIME case and that could be defined without
CONFIG_FLASH_JESD216_API being defined
Signed-off-by: Michael Larson <larson@whisper.ai>
Adjust the size of the stm32_flash_layout[] table depending on the
bank configuration of the stm32u5 or stm32l5 devices.
That will avoid div by zero error in flash_get_page_info()
if the layout_size is not correct.
Assign the *layout_size only once with the correct value : 3 or 1.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit fixes a bug in the STM32 ospi flash driver when attempting
to erase an area that spans more than one erase sector.
Without this fix, only the first sector is actually erased, the rest
silently fails the erase.
Issue is that the write enable latch command is only sent for the first
erase command.
Signed-off-by: Brian Juel Folkmann <bju@trackunit.com>
A call to exit_dpd mode for the nrf QSPI nor flash should always be
made, even if the currently executing image is compiled with
CONFIG_PM_DEVICE=n, because a previously executing image could have set
the device into DPD mode, and a call to exit_dpd is required for proper
functionality. Call `exit_dpd` regardless of the setting of
CONFIG_PM_DEVICE during QSPI nor initialization.
Signed-off-by: Nickolas Lapp <nickolaslapp@gmail.com>
Update usage of zephyr_code_relocate to follow new API. The old method
of relocating a file was the following directive:
zephyr_code_relocate(file location)
The new API for zephyr_code_relocate uses the following directive:
zephyr_code_relocate(FILES file LOCATION location)
update in tree usage to follow this model. Also, update the NXP HAL SHA,
as NXP's HAL uses this macro as well.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The find_lsb_set is giving the position of the first '1' found,
starting from 1. "Bits are numbered starting at 1
from the least significant bit."
So that the find_lsb_set(64MBytes) is 27.
The HAL_QSPI_Init() accepts Init.FlashSize where "FlashSize+1
is effectively the number of address bits
required to address the flash memory."
To get 64MBytes = 2^26, the value of the Init.FlashSize must be 25.
and bit written to the DCR = 25.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The find_lsb_set is giving the position of the first '1' found,
starting from 1. "Bits are numbered starting at 1
from the least significant bit."
So that the find_lsb_set(64MBytes) is 27.
To get 64MBytes = 2^26, the value of the Init.DeviceSize must be 26.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Change the stm32_ospi_read_sfdp to have AddressSize
prepared in one single condition.
Add more debug msg.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
During flash operation, you have to disable XiP which force function
to be located in RAM. On top of that, the function `flash_put_cmd_addr`
is time critical so we need to declare as inline. For some reason,
sometimes the function was not really inline. Changed it to
ALWAYS_INLINE fixed the bug.
Signed-off-by: Mathis Raemy <mathis.raemy@gmail.com>
Now that compatible is directly linked with driver version,
use DT compat based Kconfig flag to build the correct flash driver
version.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Instead of introducing a vX driver version, use series name.
With this commit F0, F1, F3, L0 and L1 series are using F1 flash driver.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The addresses of the flash and flash controller of the RP2040
SoC were mixed up. There was no clear distinction between the
flash and the flash controller, which was unclear but also
caused a DTC warning.
This commit makes the distinction clearer: The SSI peripheral at
0x18000000 is the flash controller, and the flash itself starts
at 0x10000000. The flash driver and rpi_pico.dts were fixed
accordingly.
Signed-off-by: Yonatan Schachter <yonatan.schachter@gmail.com>
This Kconfig is moved to the soc level since it determines
the flexspi clock initialization for XIP.
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
Clean up occurrences of "#if IS_ENABLED(CONFIG_FOO)" an replace
with classical "#if defined(CONFIG_FOO)".
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The nRF5340 product specification states that the QSPI peripheral
supports 192 MHz and 96 MHz PCLK192M frequency, thus the default /4
divider for HFCLK192M (from which PCLK192M is derived) can only be
used when the QSPI peripheral is idle. Correct the shim accordingly
and improve related comments.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
In case of errors in the status register and to
unblock Flash, it is advised to clear the errors.
Signed-off-by: Cyril Fougeray <cyril.fougeray@worldcoin.org>
`spi_is_ready` function is being deprecated in favor of
`spi_is_ready_dt` so let's replace the old usage in the tree.
Signed-off-by: Bartosz Bilas <bartosz.bilas@hotmail.com>
While diagnosing a problem on the STM32U585 in this function in
flash_stm32l5_u5.c, I had difficulty sussing out the flow of the
function and conditional logic.
This refactor seeks to improve clarity through a simplified flow control
using an early return to short circuit logic on subsequent calls to the
function and slightly more thorough comments.
Tested using tests/drivers/flash on the b_u585i_iot02a and in a
proprietary application and board which uses the STM32U585 and littlefs.
Signed-off-by: Peter Maxwell Warasila <madmaxwell@soundcomesout.com>
In flash_stm32_page_layout, the FLASH_PAGE_NB macro is used to set the
page count in the flash layout returned to the caller. On STM32L5
platforms this is defined in stm32l5xx_hal_flash.h to be (FLASH_SIZE /
FLASH_PAGE_SIZE). However, on STM32U5 platforms the macro is defined in
the soc headers (such as stm32u585xx.h) define the macro as
(FLASH_BANK_SIZE / FLASH_PAGE_SIZE). This results in the flash layout
only reflecting the first bank on STM32U5 platforms with the maximum 2
MB of flash.
This commit resolves this discrepancy by directly calculating the number
of pages by dividing FLASH_SIZE by FLASH_PAGE_SIZE.
Tested on a proprietary board using the STM32U585 which mounts a
littlefs partition in the last 256 kB of its 2 MB of flash.
Signed-off-by: Peter Maxwell Warasila <madmaxwell@soundcomesout.com>
Adaptation of the ospi nor flash driver for stm32l4 plus
where the peripheral is slighty different.
Configure the OSPIM peripheral for mcu embeddingthis peripheral
in front their octospi instances.
Add LOG for read access command like for write access.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Unlocking CR at the end of initialization was added in commit
a9183cd518. It was probably copied
from previous flash driver implementation.
Unlocking and locking CR in write and erase functions was added in
commit 6e4cdb0c99. Since we always unlock
the register before writing or erasing, and lock it after the operation
is finished, there is no need to unlock it after initialization.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Previously, while writing close to the start of flash (i.e: in the first
row), the write was never committed - due to zero being used as the
"empty buffer" marker.
This patch also incorporates some performance improvements, as well as
observing any errors reported by `flash_sam0_commit()`.
Fixes#52309
Signed-off-by: Attie Grande <attie.grande@argentum-systems.co.uk>
When the SFDP table is provided by the DeviceTree with sfdp-bfp property
It is NOT read from the octoFlash.
If no table exists in the DTS and flash read SPDP fails,
the device init fails.
Availability of this sfdp_read API is conditional
on selecting CONFIG_FLASH_JESD216_API.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit adds the jedec216 read JEDEC ID function API.
The ospi commands are issued to the octo flash device or
by the DTS jedec-id property.
Availability of this API is conditional
on selecting CONFIG_FLASH_JESD216_API.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Fixes command configuration to have samples/drivers/spi_flash
passed on stm32l562 and stm32u585 disco kits.
In OctoSPI STR/DTR and SPI/STR modes,
to determine the address_width, checking the jesd216_bfp_addrbytes
on JESD216_SFDP_BFP_DW1_ADDRBYTES_VAL_3B4B or _VAL_4B.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit set the stm32 octospi drivers for the stm32u5x
when DMA (GPDMA) is transferring.
Valid for octospi1 or octospi2.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add property mxicy,mx25r-power-mode to jedec,spi-nor binding for
controlling low power/high performance mode on Macronix MX25R* Ultra Low
Power flash devices.
- "low-power" configures the flash in ultra low power mode.
- "high-performance" configures the flash in high performance mode.
Signed-off-by: Gregers Gram Rygg <gregers.gram.rygg@nordicsemi.no>
Instead of calling __HAL_RCC_OSPIM_CLK_ENABLE() to enable the OSPI
manager clock, we now use a new clock binding in the dts.
In order to avoid confusion between the different clocks, the driver
is modified to select the clock based on their names instead of indexes.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
After a soft-reset of the host controller the flash device is not reset.
This can cause the flash device to still be busy writing or erasing when
the host controller boots and initializes the flash. The often results
in errors and the flash device not being initialized.
This fix polls the status register until the WIP flag is off before
initializing the flash device.
Fixes#51713
Signed-off-by: Gregers Gram Rygg <gregers.gram.rygg@nordicsemi.no>
Adds Atmel SAMC20 and SAMC21 soc. C series is based on Cortex-M0+.
C21 contains CAN interface.
The init routines are same for SAMC20 and SAMC21. They use one
clock OSC48M without configuration.
The code is inspirated from atmel_sam0/samd21.
Signed-off-by: Kamil Serwus <kserwus@gmail.com>
Executing code out of RAM on IT8xxx2 requires that the relevant
addresses be mapped onto the CPU's instruction memory bus, referred to
by ITE documentation as Instruction Local Memory (ILM). ILM mappings
configure blocks of RAM to be used for accesses to chosen addresses when
performing instruction fetch, instead of the memory that would normally
be accessed at that address.
ILM must be used for some chip features (particularly Flash
self-programming, to execute from RAM while writing to Flash), and has
historically been configured in the Flash driver. The RAM for that was
hard-coded as a single 4k block in the linker script. Configuring ILM
in the flash driver is confusing because it is used by other SoC code as
well, currently in code that cannot depend on the Flash being functional
or in hand-selected functions that seem performance-critical.
This change moves ILM configuration to a new driver and dynamically
allocates RAM to ILM in the linker script, allowing software use of the
entire 64k RAM depending on configuration. This makes ILM configuration
more discoverable and makes it much easier to correctly support the
CODE_DATA_RELOCATION feature on this SoC.
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Fixes build of flash_shell sample after commit
a6a4400b86.
west build -p -b xmc45_relax_kit samples/drivers/flash_shell
Also include stdint.h.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
Change automated searching for files using "IRQ_CONNECT()" API not
including <zephyr/irq.h>.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
On stm32g0, stm32g4, stm32l4, stm32l5, stm32u5,
and stm32wbx, it is allowed to write a zeroed dword
on unerased flash.
Signed-off-by: Cyril Fougeray <cyril.fougeray@worldcoin.org>
We have been encountering timeout issues when erasing large flash
sections (before receiving an image via mcuboot) from this semaphore
take:
5af0fbc2e3/drivers/flash/soc_flash_nrf_ticker.c (L225-L233)
I think this is because this constant is based on the time taken to erase
the chip but doesn't take account of the fact it is being done by a
ticker. If I understand correctly the ticker is a timeshare mechanism
so the actual max erase time is some factor based on how much time is
given to the task by the ticker.
This multiplies the max timeout by 1.5
Signed-off-by: Kyle Cooke <cookekyle97@gmail.com>
Fix the scope of some variables in various STM32 drivers including:
- SDMMC
- DMA
- OSPI/QSPI Flash
- Interrupt controller
The variables are set static instead of global and const if appropriate.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
With the incoming removal of kernel.h/types.h from init.h, lots of files
start to show compile errors because they relied on indirect
definitions, including errno.h.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
If the flash is used in 4-byte addressing, reading SFDP will fail after
a system reset if the flash isn't power cycled or hardware reset, since
Zephyr will try to use 3-byte addressing while the flash (still) expects
4-byte addressing.
This commit adds the ability to send a reset command to the flash as part
of initialization, which complements the existing reset-gpio
functionality, and is useful on low-pincount flashes which do not have a
hardware reset.
Signed-off-by: Ole Morten Haaland <omh@icsys.no>
Change reduces time consumed when a block needs to be erased.
The change was tested on a mimxrt1060_evk board.
Signed-off-by: Dipak Shetty <dipak.shetty@zeiss.com>
This commit adds two new commands to flash shell tools: flash load and
flash page_info.
Signed-off-by: Franciszek Zdobylak <fzdobylak@internships.antmicro.com>
It's useful for RAMABLE_REGION to have a uniform name when
CODE_DATA_RELOCATION is supported, because otherwise the build system
needs to be aware of how the region name differs between architectures.
Since architectures tend to prefer one of 'SRAM' or 'RAM' for that
region, prefer to use 'RAM' as the more general term.
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Fix the issue that the initialization will fail when both
CONFIG_SPI_NOR_SFDP_RUNTIME and CONFIG_SPI_NOR_IDLE_IN_DPD are enabled.
The cause of this problem is simply calling the wrong function.
Fixes#33015
Signed-off-by: Xinyang Tan <xinyang.tan@delve.com>
Introducing the dma transfer (also through dmamux)
to transfer data to/from the NOR octo-flash
With a DMAMUX, the DMA channel is given by the DTS.
Note that STM32U5X does not support DMA here.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This supports three types GD32 FMC flash memory. GD32 FMC v1,
GD32 FMC v2 and GD32 FMC v3.
GD32 FMC v1 for small flash memory, flash size can be up to 512KB.
GD32 FMC v2 for large flash memory, flash size can be up to 3072KB.
GD32 FMC v3 not use page but sector as minimum block, flash size can
be up to 3072KB.
Signed-off-by: HaiLong Yang <hailong.yang@brainco.cn>
Ticker stop callback are executing in ULL_HIGH priority,
correct the value to 1U instead of 0U which is for LLL
execution context of the Bluetooth Controller.
Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
Fix usage fault due to spurious ticker timeout expiry post
enqueuing of ticker stop operation.
Use ticker operation callback to handle completion of ticker
stop operation and then give the semaphore to thread to
notifying the completion of flash operation.
Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
As of today <zephyr/zephyr.h> is 100% equivalent to <zephyr/kernel.h>.
This patch proposes to then include <zephyr/kernel.h> instead of
<zephyr/zephyr.h> since it is more clear that you are including the
Kernel APIs and (probably) nothing else. <zephyr/zephyr.h> sounds like a
catch-all header that may be confusing. Most applications need to
include a bunch of other things to compile, e.g. driver headers or
subsystem headers like BT, logging, etc.
The idea of a catch-all header in Zephyr is probably not feasible
anyway. Reason is that Zephyr is not a library, like it could be for
example `libpython`. Zephyr provides many utilities nowadays: a kernel,
drivers, subsystems, etc and things will likely grow. A catch-all header
would be massive, difficult to keep up-to-date. It is also likely that
an application will only build a small subset. Note that subsystem-level
headers may use a catch-all approach to make things easier, though.
NOTE: This patch is **NOT** removing the header, just removing its usage
in-tree. I'd advocate for its deprecation (add a #warning on it), but I
understand many people will have concerns.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
In case SFDP table is provided via device tree, take care not reading
more than expected by the function caller as the result is written
in a structure which size is predefined by one specific byte in the
table, and could be smaller than the table size.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
NSEC_PER_MSEC should be defined along with the rest of the
per-sec macros in sys_clock.h. Currently, it's defined
multiply in a few separate locations.
Signed-off-by: Christopher Friedt <cfriedt@fb.com>
This adds flash driver for Renesas SmartBond(tm) family.
This technically uses QSPI controller but since default and most
commonly used configuration is to boot from external QSPI flash (DA1469x
do not have built-in flash) and that flash is mapped into memory space,
it can be represented as internal flash.
Signed-off-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
Signed-off-by: Ben Lauret <ben.lauret.wm@renesas.com>
When configuring the octo-flash in SPI/STR mode, the address size
must be on 24bits (and not on 32bits).
Despite the dev_data->address_width which is always seen as 4, the
erase command must reduce the AddressSize for this transfer mode.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit enables the SoC's flash memory controller.
- added lpc55s36 specific code in the NXP MCUX driver
to take advantage of the SoC's check-before-read
capability
- enabled the FMC node in the SoC's dtsi (iap)
- added the flash controller chosen node to the board's dts
Signed-off-by: Yves Vandervennet <yves.vandervennet@nxp.com>
Add support for LPC54xxx IAP flash driver to soc_flash_lpc.c
Driver is tested on M4 core only, and is therefore disabled on the M0 core.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Use correct printf format specifier for LOG_DBG calls using offsets, as
these offsets are long int and thus require the %lx format specifier rather
than %x.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Many device pointers are initialized at compile and never changed. This
means that the device pointer can be constified (immutable).
Automated using:
```
perl -i -pe 's/const struct device \*(?!const)(.*)= DEVICE/const struct
device *const $1= DEVICE/g' **/*.c
```
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
It is frequent to find variable definitions like this:
```c
static const struct device *dev = DEVICE_DT_GET(...)
```
That is, module level variables that are statically initialized with a
device reference. Such value is, in most cases, never changed meaning
the variable can also be declared as const (immutable). This patch
constifies all such cases.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Remove flash driver dependency on CONFIG_HAS_MCUX_IAP for determining
if the SOC uses an NXP IAP flash controller, and instead use the
devicetree compatible to determine this.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The binding 'nxp,lpc-iap' is no longer used, which is confirmed
by running:
$ find ${ZEPHYR_BASE}/dts/arm/nxp -type f | egrep -e '\.dts(i)*$' | \
xargs grep -nH nxp,lpc-iap
Changes in this commit:
- remove DT_HAS_NXP_LPC... in drivers/flash/Kconfig.mcux
- remove schema file for nxp,lpc-iap
Signed-off-by: Yves Vandervennet <yves.vandervennet@nxp.com>
The lpc and mcux drivers' DRV_COMPAT is updated for the new bindings
introduced in the previous commit. The drivers' Kconfig files also
reflect this change (DT_HAS_ENABLED_NXP_...).
The SoC device trees are updated with the new bindings
Signed-off-by: Yves Vandervennet <yves.vandervennet@nxp.com>
Do simple conversion of driver to have driver enabled by devicetree
in Kconfig and struct device created based on basic devicetree
data.
Signed-off-by: Kumar Gala <galak@kernel.org>
The current atmel sam flash driver was develop based on the cortex-m7
version of smart arm microcontroller. The driver support write
protection and cache functions which is not supported by other cortex-m
variants. This fixes current driver implementation and devicetree
entries for all sam variants.
Notes:
* The cortex-m3 doesn't have support erase pages flash command and
because of that the driver still not not compatible. Keep it disabled
until a patch be send. The hwinfo driver is not affected by this
restriction.
* The sam4l variation requires a specific driver because uses another
flash controller (flashcalw). Added another compatible to
differentiate and keeped node disabled until a driver be available.
Fixes#48516
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Fixes command configuration to have samples/drivers/spi_flash
passed on stm32l562 and stm32u585 disco kits.
In OctoSPI STR/DTR and SPI/STR modes
Signed-off-by: Francois Ramu <francois.ramu@st.com>
In the continuation of the previous commit, replace _OPT_ by _DOMAIN_
in macros relating to this feature.
hen, adapt drivers and tests to this new wording.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Update flash drivers to use DT_HAS_<compat>_ENABLED Kconfig symbol
to expose the driver and enable it by default based on devicetree.
We remove 'depend on' Kconfig for symbols that would be implied by
the devicetree node existing.
Signed-off-by: Kumar Gala <galak@kernel.org>
With the introduction of the OSPI NOR flash controller
the stm32H7 serie requires the HAL MDMA in anycase.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
MISRA C:2012 Rule 14.4 (The controlling expression of an if statement
and the controlling expression of an iteration-statement shall have
essentially Boolean type.)
Use `do { ... } while (false)' instead of `do { ... } while (0)'.
Use comparisons with zero instead of implicitly testing integers.
The commit is a subset of the original auditable-branch commit:
5d02614e34a86b549c7707d3d9f0984bc3a5f22a
Signed-off-by: Simon Hein <SHein@baumer.com>
Fix building this sample on bl5340_dvk_cpuapp_ns and
pinnacle_100_dvk. On these boards the NORDIC_QSPI_NOR
driver needs to be enabled for the sample to build.
Signed-off-by: Kumar Gala <galak@kernel.org>
When using the settings subsystem, the data argument argument passed to
flash_stm32_write_range() might not be 8-bytes aligned, causing an
unaligned memory access fault.
Fix that the same way as it was done for the STM32L4 in commit
652efa530f.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Following zephyr's style guideline, all if statements, including single
line statements shall have braces.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The clock of the octospi peripheral is directly defined
by the DTS and configured by the clock_control_on function.
No specific stm32cube function is required then.
The clock control is taking this clock source to calculate
the clock rate.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This adds a table to set the dma channel priority from the DTS
The config bits are converted through the table_priority
to match the DMA_Priority_level of the stm32cube HAL.
Fixes#46725
Signed-off-by: Francois Ramu <francois.ramu@st.com>
wait_write_queue() get passed a device and an offset to compute the
sector number and verify it is valid. However both operations are
already done by the caller, so let's pass directly the
flash_stm32_sector_t value instead.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
The STM32H7 flash driver read-back a register after writing it to ensure
it is flushed. This is very fragile and might break if a new compiler
version slightly reorder the instructions. Instead use a __DSB()
barrier like done on other STM32 SoC, which ensures that the registers
and the data writes are flushed at the compiler level, but also at the
Cortex-M7 level.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
As the erase time for a sector differs by a few order of magnitude for the
various SoCs of the STM32H7 family, use the just added max-erase-time
property from the device tree instead of the hard-coded 4 seconds value.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Support writing to NOR-Flash over OSPI using
the following modes:
* 1-1-1
* 1-1-4
* 1-4-4
Supports 4-Byte opcodes conversion for write opcodes.
Allows users to set what write/program opcode is used
in the DTS (not for OPI mode).
Will use some default PP opcodes based on the mode.
Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
Adds support to read and erase NOR-Flash over OSPI using
the following modes:
* 1-1-2
* 1-2-2
* 1-1-4
* 1-4-4
Supports 4-Byte opcodes conversion and gets address width
from the SFDP:BFP.
Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
Adds:
* PP and Read 4-Byte command defines
* PP 1-1-2 define
* Missing 1-2-2 (0xBB) and Read Fast (0x0B) command defines
Re-arranges the commands so that they stay in order.
Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
When defined as 'char', the compiler notices that the memcpy targeting that
address will write more than one byte which generates a warning. Use an
array instead so that the compiler doesn't assume a specific size.
Signed-off-by: Keith Packard <keithp@keithp.com>
- The MX25UM51345G flash is connected to FLEXSPI PortA for
mimxrt595_evk.
- Updated flexspi_mx25um51345g driver to support DTR OPI mode.
- Tested with tests/drivers/flash.
Signed-off-by: Chay Guo <changyi.guo@nxp.com>
This includes a basic driver for built-in flash on the Texas Intruments
SimpleLink CC13xx/CC26xx SoC series.
The driver makes use of driverlib HAL from TI's SDK and was tested on
two LaunchXL development boards with CC1352R and CC2652R SoCs:
- CC1352R1 LaunchXL
- CC26x2R1 LaunchXL
Tests were done using:
- flash shell sample (samples/drivers/flash_shell)
- littlefs filesystem sample (samples/subsys/fs/littlefs)*
- MCUboot (bootloader/mcuboot/boot/zephyr)*
* additional changes in DTS for the boards were required (partitions
table) and are not part of this changeset (will be introduced later)
Some additional information about the implementation:
1. TI's Technical Reference Manual for CC13x2 and CC26x2 points out that
"An individual 64-bit word can be programmed to change bits 1 to 0"
but it seems this 'alignment' requirement is handled internally by
the ROM function and thus 'write-block-size' is set to 1.
2. Interrupts, VIMS and line buffers are disabled during flash content
update (write or erase) and restored afterwards as recommended by TI.
3. Only RAM to flash write is supported (source of data to be written to
flash can't point to flash).
4. The driver doesn't take care of flash sector protection disable as
that functionality is handled by CCFG. Write or erase requests which
refer to a protected area will fail.
Signed-off-by: Piotr Dymacz <pepe2k@gmail.com>
anomaly_122_init() and anomaly_122_uninit() procedures implement
proper activate and deactivate procedures which are required for
achieve low power consumption.
The real workaround for the anomaly is buried inside hal function
nrf_qspi_disable() is called indirectly by the anomaly_122_uninit().
Therefore anomaly_122_init/uninit should be called for any
nrf QSPI device.
This patch renames functions and make call to them mandatory.
This fixes increased power consumtion issue on nRF53 device when
qspi was used.
Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
The flash_stm32_write_range() function of the STM32H7x flash
driver partially uses a wrong flash program word size for certain
SOC types when calculating the flash write offset. If the used
SOC is not having a flash program word size of 256 bits / 32 bytes
the written data might get corrupted, as the flash write offset
value does not match the number of bytes that were actually
written.
Fixes#45568
Signed-off-by: Christoph Heller <chris@metanetics.de>
There is no need in the `flag_quad_io_en` field.
When QE enabling failed, then the driver `init` fails as well.
There is no way to use qspi in quad mode if qe is not enabled.
Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
Adds support for 1-4-4 and 1-1-4 read modes.
SFDP is used to query for available read instructions, then the
fastest one is used.
Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
* Renames 4PP define to PP_1_4_4
* Adds PP_1_1_4 define
That matches linux kernel defines a bit more.
Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
Simplifies the driver and Gives a generic function to prepare the Regular
commands for each instruction.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This is the stm32 octospi driver based on the exisitng quadspi
for stm32 devices and source code from the STM32Cube.
This drivers initialized the peripheral and the NOR memory
in SPI or OctoSPI mode with STR or DTR data Transfer rates.
The NOR-flash can provide the SDFP table directly (if supported)
or through the DeviceTree.
Limitation: no DMA transfer.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
With the introduction of the OSPI NOR flash controller
more octal commands and parameters are defined.
It completes the existing SPI commands
Signed-off-by: Francois Ramu <francois.ramu@st.com>
In order to bring consistency in-tree, migrate all drivers to the new
prefix <zephyr/...>. Note that the conversion has been scripted, refer
to #45388 for more details.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Do not default FLASH_MCUX_FLEXSPI_XIP to enabled when code is not
located in flash, this will cause issues if code is executing from ITCM,
as the zephyr_code_relocate macro will relocate the flash driver code
into itcm, and overwrite the zephyr image.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
since the flexspi driver interacts with the flash device, storing
device data in flash can cause RWW hazards when running in XIP mode.
Move all device data to RAM to limit these RWW hazards.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
since the flexspi driver interacts with the flash device, storing
device data in flash can cause RWW hazards when running in XIP mode.
Move all device data to RAM to limit these RWW hazards.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Move all device data to RAM. Since the flexspi driver accesses the
flash device that is being used for XIP, various RWW hazards can occur
if the flexspi driver is interacting with the flash device, while
running in XIP mode.
Fixes#45182
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This modification is required to enable flash encryption.
Using hal implementation of spi_flash calls maintains
compability amongs different socs while offering
latest esp-idf enhancements.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add a check to avoid invalidating the cache when the latter is disabled.
Indeed, doing so can lead to a bus fault.
Signed-off-by: Thomas Altenbach <taltenbach@witekio.com>
redefine all the stm32 flash register bit Name from
FLASH_NSCR_xxx to FLASH_STM32_FLASH_NSCR_xxx
in all the zephyr drivers.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Adds the stm32u5 flash controller driver for this serie
to the existing stm32l5 flash driver part
Only 1 or 2 MB devices exist today (4MB is possible in the future).
This flash controller driver is adapted from the flash_stm32l5.c
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This adds the stm32U5 soc family to the flash driver
The flash controller has particular register names in the Non-Secure
area to be adapted for the driver.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The cmd_write contains write verification that compares what has
been written with what it can read; the flash read operation
status was not checked which means that the bus or communication
problem was reported the same way as malformed write.
There have also been some optimization done by removal
of multiplications.
Signed-off-by: Dominik Ermel <dominik.ermel@nordicsemi.no>
The commit changes default buffer size for flash write operations
to be CONFIG_SHELL_ARGC_MAX dependent; there is no point to define
buffer longer than number of write bytes that will be extracted
from command line arguments.
Signed-off-by: Dominik Ermel <dominik.ermel@nordicsemi.no>
Store an optional reference to the zephyr,flash-controller choice. If
available and no user input is provided, it will be used as the default
flash device. If not available, error message will be more explicit.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Add support for S2B1 quad-enable-requirements.
Add wrsr call for various QER modes
S2B1v6 mode tested with Winbond W25Q128JV series and pp4o and read4io
commands.
Signed-off-by: Zack Cornelius <zcornelius@securityesys.com>
Added basic support for enter 4-byte addressing command.
Patch supports command 0xB7 (Enter 4-Byte Address Mode),
with or without preceding WREN.
Similar as for SPI-NOR the `enter-4byte-addr` property of
memory node is used or describing how to Enter 4-Byte Addressing
mode.
Worth to notice that along with that property the `address-size-32`
property is expected as it switch the driver to use 4-byte addressing
in operations.
Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
The Kconfig function "dt_node_has_prop" was using label as its
parameter, where other functions use either chosen or path.
The documentation says that the parameter is path, so this patch
makes the function as documentation says and as other functions
in the file.
The additional nodelabel functions were added as counterparts that
are using nodes labels instead of paths.
Signed-off-by: Michał Barnaś <mb@semihalf.com>
If a user has a 1GB external flash it is currently not possible
to configure this through DTS. To allow for such a configuration
we add an option which specifies the size in bytes not bits.
Signed-off-by: Håkon Øye Amundsen <haakon.amundsen@nordicsemi.no>
flexspi driver should not interact with flash whenever possible, and
should never use flash while in a critical write or erase section.
Move device data to RAM to prevent this read-while-write hazard.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
flexspi driver should not interact with flash whenever possible, and
should never use flash while in a critical write or erase section.
Move device data to RAM to prevent this read-while-write hazard.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
flexspi driver should not interact with flash whenever possible, and
should never use flash while in a critical write or erase section. Move
device data to RAM to prevent this read-while-write hazard.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Extend the macro with checks for DT properties related to pin
assignments that are defined but would be ignored, depending on
whether PINCTRL is enabled or not, what presumably indicates
a resulting configuration different from what the user expects.
Add also a possibility to indicate that the pinctrl-1 property
should not be checked because the caller does not support the
sleep state.
Rename the macro so that its name better reflects its function.
Update accordingly all drivers that use it.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
A nordic hal update was made around the same time that anomaly 122 on
nrf52840 was fixed. This update introduced qspi_pins_deconfigure() in
the nrfx_qspi_uninit(). With that, the CS pin from QSPI becomes a
floating pin after anomaly 122 uninit is executed.
Set the CS pin high after the uninit to fix this.
I'm assuming that floating CS pins that are likely to experience EMI
can impact power consumption. That was the case with my custom board.
My custom board with nrf52840 and MX25R3235F running the hello_world
sample was consuming 2.3 mA before this patch, and 30 uA after
applying it.
Signed-off-by: Rodrigo Brochado <git.rodrigobrochado@gmail.com>
This API has be removed in Zephyr 2.8, and does not need to be used
as a static function. Because flash_it8xxx2_write_protection(false)
is not supported. If the IT83XX_GCTRL_EPLR register in the
flash_it8xxx2_write_protection(false) is written as 1, the flash
write region will not be protected later, only be cleared by
power-on reset.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Just use dev->name. This change follow same principles applied when
DEV_CFG and DEV_DATA macros were removed.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Add support for the new pinctrl API to the nRF QSPI NOR flash driver.
Update code of the driver and the related devicetree binding.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
It may happen that after the flash chip was previously put into
the Deep Power Down mode, the system was reset but the flash chip
was not. Consequently, the flash chip can be in the DPD mode when
the QSPI driver is initialized. Some flash chips will just exit
the DPD mode on the first CS pulse, but some need to receive the
dedicated command to do it and they will not respond to any other
commands including those that the driver need to perform to complete
its initialization ("Read status register" and "Read JEDEC ID").
This commit adds sending of the "Release from Deep Power Down"
command right after initialization of the QSPI interface to avoid
the problem described above.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
According to Kconfig guidelines, boolean prompts must not start with
"Enable...". The following command has been used to automate the changes
in this patch:
sed -i "s/bool \"[Ee]nables\? \(\w\)/bool \"\U\1/g" **/Kconfig*
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Controller device can be obtained at compile time, so make
implementation more efficient thanks to that.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Controller device can be obtained at compile time, so make
implementation more efficient thanks to that.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The controller device instance can be obtained at compile time using
DEVICE_DT_GET, so do that.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
STM32L5 has option to disable dual bank support.
When this is disabled, the flash page size is changed
from 2k pages to 4k pages. This PR adds support for this
diversity.
Signed-off-by: Wouter Cappelle <wouter.cappelle@crodeon.com>
Restore the testcase to run on the qspi nor-flash controller
of the disco_l475_iot1 board
of the disco stm32f746 board
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Like the stm32 flash driver, in case of QSPI nor flash controller
the read or write or erase returns '0' if data is of null size.
This avoids useless QPSI low level access to the controller.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The handler was reworked to internal function and it
is called from the erase and the write
procedures automatically now.
This change was made due to deprecation of the flash write-protection
API.
Explanation for so late removal:
Reworked callback was introduced despite that the API had been
already deprecated at the addition time.
Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
On nRF53 Series SoCs, the highest SCK frequencies can only be achieved
when the HFCLK192M clock divider is changed from the default /4 setting.
Such change results in increased power consumption, so the divider needs
to be changed only for periods when it is actually necessary.
This commit modifies the driver behavior so that it changes the divider
only when a QSPI bus operation is performed.
However, when XIP accesses to the flash chip are also used, it may be
needed to keep the divider changed even when the driver is idle so that
the XIP access speed is not reduced, hence a custom API function that
allows forcing this is introduced for the driver.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Address the issue mentioned in zephyrproject-rtos#7412
Using printf() with "%x" to print an off_t value produces the
following warning:
format '%x' expects 'unsigned int', argument has type 'long int'
228 | LOG_DBG("Erasing sector at 0x%08x", offset);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~
| |
| off_t {aka long int}
In newlib off_t is long. Even though both int and long are 4 bytes wide
in the architecture in use, GCC wants to see "%lx" to printf() a long.
Using "%"PRIx32 still produces the same warning because PRIx32
(from inttypes.h) still expands to simply an "x" and not "lx".
PR zephyrproject-rtos#40004 has solved this by casting offset to
ssize_t. The same solution is emulated here.
Signed-off-by: Milind Paranjpe <milind@whisper.ai>
Replace all get_dev_data()/get_dev_config() accessor utilities with
dev->data and dev->config.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Stop using redundant DEV_DATA/DEV_CFG macros and use dev->data and
dev->config instead.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
In order to align with macros used to obtain a device reference (e.g.
DEVICE_DT_GET), align the PM macros to use "GET" instead of "REF". This
change should have low impact since no official release has gone out yet
with the "REF" macros.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Refactors all of the on-chip flash drivers to use a shared driver class
initialization priority configuration, CONFIG_FLASH_INIT_PRIORITY, to
allow configuring flash drivers separately from other devices. This is
similar to other driver classes like I2C and SPI.
The default is set to CONFIG_KERNEL_INIT_PRIORITY_DEVICE to preserve the
existing default initialization priority for most drivers.
Driver-specific options for SPI-based flash drivers are left intact
because they need to be initialized at a different priority than on-chip
flash drivers.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
We will soon need to do more boundary checking to test whether we are
reading secure or non-secure memory.
Refactor the boundary checking in preparation for this.
Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
This change provides support for 4 IO read (via 4READ command) and
program (via 4PP). Flash memory pins SIO[0123], CLK and CS are used.
All of them are controlled by stm32 QSPI IP block.
The instruction code for fast reading as well as number of latency
cycles required are read from SFDP structure provided by flash memory.
The number of required read latency cycles when performing reading
is the sum of SPI-NOR memory mode bits and wait states (also named
as 'dummy cycles').
It also has been assumed that memory, which supports fast read (4READ),
also will support fast programming (4PP command) as this information is
not available in SFDP.
One also need to enable the QUAD IO support in board's device tree by
defining 'spi-bus-width = <4>' property. It is required as it may
happen that not all QSPI dedicated pins are used (for example only two
of them are available).
Signed-off-by: Lukasz Majewski <lukma@denx.de>
For proper operation of QUADSPI IP block, both sides of communication;
NOR flash memory and STM32 controller need to support 4 IO
transmission.
After this change the QSPI stm32 driver is able to program NOR flash
memory to switch itself to use all 4 IO lines (SIO[0123]) to transmit
and receive data.
The QE bit (in SPI-NOR's Status Register) is the non-volatile one, so
setting it is done only once (at first boot of the device).
Signed-off-by: Lukasz Majewski <lukma@denx.de>
This commit provides define for reading the control register (CR) on
the flash memory.
In that register the information about 4B addressing is stored.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
