Fix issues reported by string validation which was added to strings
used in zassert macros.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
These two tests are validating that deprecated APIs still work
correctly. Which means they will definitely generate compile warnings.
To disable -Werror while letting it be enabled for other tests, create a
new Kconfig variable, DEPRECATION_TEST and make
COMPILER_WARNINGS_AS_ERRORS depend on that option being unselected. Add
this option to the two tests so that the resulting configuration
disables -Werror.
Signed-off-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The new Nordic platforms use GRTC instead of RTC
as the system timer.
Also the nrf54h20 CPUPPR target does not have enough memory
to execute the `timer_behavior` test.
Signed-off-by: Adam Kondraciuk <adam.kondraciuk@nordicsemi.no>
Picolibc changed things like _WANT_MINIMAL_IO_LONG_LONG to
__IO_MINIMAL_LONG_LONG in an attempt to regularize the exposed names and
eliminate names that weren't prefixed with even a single underscore.
Adapt to this change by looking for both old and new symbols.
Signed-off-by: Keith Packard <keithp@keithp.com>
Turns off time slicing as these tests do not expect time slicing and
previously operated without time slicing, but now fallback to the new
default of a time slice size of 20 added in e337b7b. This explicitly sets
the time slice size to 0.
Signed-off-by: Daniel Mangum <georgedanielmangum@gmail.com>
Sets CONFIG_TIMESLICE_SIZE=0 for tests that previously expected to run
without timeslicing enabled, and now fail with the default
CONFIG_TIMESLICE_SIZE=20. Note that timeslicing functionality is still
included, but no actual timeslicing is performed.
Signed-off-by: Daniel Mangum <georgedanielmangum@gmail.com>
According the specification, in extreme cases, the deviation of the APB
clock and LFCLK clock can reach up to +/-1% (+/- 10ms).
Therefore, exclude npcx platforms from the test because it required 1ms
accuracy.
fixes: #66185
Signed-off-by: Arkadiusz Cholewinski <arkadiuszx.cholewinski@intel.com>
Due to the constant alloc/free cycles during the stress test,
it is possible that the heap can become fragmented enough to
prevent successful allocation, and thus failing the test.
So we change the CONFIG_SYS_HEAP_ALLOC_LOOPS to a higher value
so the allocation code will try harder to find a space.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
There are lots of copy and paste error message which does not
really tell you which part fails. So make those messages more
explcitly on where it is emitting the error message.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The syscall stress test relies on timeslicing to switch between
threads, which utilizes the interrupt handling path to perform
context switching. It is also possible for kernel to switch
threads due to, for example, taking a mutex. This adds a bit of
code to the syscalls test to simulate this by yielding while
inside syscall handlers. This is to cover more scenarios so we
can catch issues earlier.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Add a loop to join the stress threads after calling abort.
This is to make sure all stress threads have already stopped
before moving on. Simply for test hygiene.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This moves the syscall torture test into another test group or
suite so that we run the individual syscall tests first before
the torture test. If individual test fails, it is easier to see
the error. Especially under SMP where multiple CPUs can report
the same error, cluttering the output.
Also rename the test to syscall_switch_stress to better describe
its purpose.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This modifies string_copy() to have an addition ID as function
argument so that it can copy into different buffers during
the multi-threaded stress test, instead of all threads writing
into the same buffer. This is to prevent a situation where
one thread writes incorrect data but being overwritten by
another thread with correct data, thus making the following
strcmp() passing for both threads. Logically this should never
happen since the same function is being called which should
give same result, but it is simply to test for weird
situations.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This commit resolves lock contention
issues by increasing the probablity of
contention during the test execution.
Increased wait delay when lock is taken
and Reduced wait delay when the lock is
released.
Achieved 99% lock contention probablity,
verified through runtime metrices.
Signed-off-by: S Swetha <s.swetha@intel.com>
Extend timeout on k_mem_slab_alloc() for kernel.memory_slabs
memory_slab_1cpu.mslab test suite as a workaround to allow its run
on slow platforms, e.g. simulated intel_ish_5_8_0.
Signed-off-by: Dmitrii Golovanov <dmitrii.golovanov@intel.com>
Check the order of constructors, making sure those with a specified
priority are called in numeric order after which those without priority are
called.
Signed-off-by: Keith Packard <keithp@keithp.com>
Add return value to z_add_timeout. It returns system tick when timeout
will expire.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Validate that `K_TIMEOUT_ABS_SEC` works the same way as the other
absolute timeout construction macros.
Signed-off-by: Jordan Yates <jordan@embeint.com>
According the specification, in extreme cases, the deviation of the APB
clock and LFCLK clock can reach up to +/-1% (+/- 10ms).
Therefore, exclude npcx platforms from the test because it required 1ms
accuracy.
fixes: #66185
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
This patch allows checking for any custom ARM interrupt controller to get a
non-enabled IRQ line instead of assuming that GIC is enabled
Signed-off-by: Amneesh Singh <a-singh7@ti.com>
Some platforms were excluded due to issues that were fixed or resolved
themselves. Enable those platforms again and remove the comments related
to the issues.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Test was assuming that CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 but such
frequency is not well supported on SoC which are based on 32768 Hz RTC
clock. Align test to be able to work with different sys_clock
frequency by converting previously 20 ticks to milliseconds.
Set CONFIG_SYS_CLOCK_TICKS_PER_SEC=32768 when system clock is using
Nordic RTC timer driver.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Type case CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC to uint32_t
while defining sys_clock_hw_cycles_per_sec_runtime_get()
to extend the range of frequency to 0xffffffff.
Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
k_thread_priority_set() on a pended thread wasn't re-inserting into the
waitq, causing the incorrect thread to run based on priority. When using
the scalable waitq config, this can also break assumptions of the tree
and leave the owner of a waitq still being in the waitq tree, cycles in
the tree, or a crash.
Remove and re-add a thread to a waitq to ensure the waitq remains in
order and the tree's assumptions are not violated.
To illustrate the issue, consider 4 threads in decreasing priority
order: A, B, C, and D along with two mutexes, m0 and m1. This is
implemented in the new complex_inversion mutex_api test.
1. D locks m1
2. C locks m0
3. C pends on m1
4. B pends on m1
5. A pends on m0, boosts C's priority, now tree on m1 is not sorted
6. D unlocks m1, left-most thread on tree is B. When removing B from
tree it cannot be found because it searches to the right of C due to
C's boosted priority when the node is actually on the left. rb_remove
silently fails.
7. B unlocks m1, left-most thread on tree is still B and it tries to
unpend itself, resulting in a NULL pointer dereference on
B->base.pended_on.
Signed-off-by: Josh DeWitt <josh.dewitt@garmin.com>
Make sure we install packages with no issues, some of the issues being
reporting on packages we might install using pip:
Warn: Project is vulnerable to: PYSEC-2019-41 / GHSA-qfc5-mcwq-26q8
Warn: Project is vulnerable to: PYSEC-2014-14 / GHSA-652x-xj99-gmcc
Warn: Project is vulnerable to: GHSA-9wx4-h78v-vm56
Warn: Project is vulnerable to: PYSEC-2014-13 / GHSA-cfj3-7x9c-4p3h
Warn: Project is vulnerable to: PYSEC-2018-28 / GHSA-x84v-xcm2-53pg
Warn: Project is vulnerable to: PYSEC-2017-74
Warn: Project is vulnerable to: GHSA-55x5-fj6c-h6m8
Warn: Project is vulnerable to: PYSEC-2014-9 / GHSA-57qw-cc2g-pv5p
Warn: Project is vulnerable to: PYSEC-2021-19 / GHSA-jq4v-f5q6-mjqq
Warn: Project is vulnerable to: GHSA-pgww-xf46-h92r
Warn: Project is vulnerable to: PYSEC-2022-230 / GHSA-wrxv-2j5q-m38w
Warn: Project is vulnerable to: PYSEC-2018-12 / GHSA-xp26-p53h-6h2p
Warn: Project is vulnerable to: PYSEC-2024-4 / GHSA-2mqj-m65w-jghx
Warn: Project is vulnerable to: PYSEC-2023-165 / GHSA-cwvm-v4w8-q58c
Warn: Project is vulnerable to: PYSEC-2022-42992 / GHSA-hcpj-qp55-gfph
Warn: Project is vulnerable to: PYSEC-2023-137 / GHSA-pr76-5cm5-w9cj
Warn: Project is vulnerable to: PYSEC-2023-161 / GHSA-wfm5-v35h-vwf4
Warn: Project is vulnerable to: GHSA-3f63-hfp8-52jq
Warn: Project is vulnerable to: GHSA-44wm-f244-xhp3
Warn: Project is vulnerable to: GHSA-56pw-mpj4-fxww
Warn: Project is vulnerable to: GHSA-j7hp-h8jx-5ppr
Warn: Project is vulnerable to: PYSEC-2023-175
Warn: Project is vulnerable to: PYSEC-2018-34 / GHSA-2fc2-6r4j-p65h
Warn: Project is vulnerable to: PYSEC-2021-856 / GHSA-5545-2q6w-2gh6
Warn: Project is vulnerable to: PYSEC-2019-108 / GHSA-9fq2-x9r6-wfmf
Warn: Project is vulnerable to: PYSEC-2018-33 / GHSA-cw6w-4rcx-xphc
Warn: Project is vulnerable to: PYSEC-2021-857 / GHSA-f7c7-j99h-c22f
Warn: Project is vulnerable to: GHSA-fpfv-jqm9-f5jm
Warn: Project is vulnerable to: PYSEC-2017-1 / GHSA-frgw-fgh6-9g52
Warn: Project is vulnerable to: GHSA-c6fm-rgw4-8q73
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The TOOLCHAIN_DISABLE_WARNING/TOOLCHAIN_ENABLE_WARNING macros are easier
to read and compiler agnostic.
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Add some overlay files for the silabs xg29_rb4412a board to enable tests
on the board. Also add the platform to some testcase.yaml files.
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
Some projects may have needs for more than 99 priority levels, so add
a third linker input section for each obj level.
Signed-off-by: Josh DeWitt <josh.dewitt@garmin.com>
Several devices have hardware-specific additional limits for
how short a sleep cycle can be. Add an entry for devices based
on Silabs sleeptimer when the OS tick rate is equal to the timer
frequency.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
