Simplified handling of runtime filtering that lead to removal
of LOG_CHECK_CTX_LVL_FILTER macro. Fixing multiply coverity issues
like CID 236013.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
use atomic_clear_bit instead of atomic_test_and_set_bit
which will not return old value, and thus more coverity friendy
Fixing: #35154
Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
Arg can be double * and it is casted to int *. Coverity reports
it (CID 235943). Fixed by adding intermediate void * variable.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
The naming and documentation of the parameters was inconsistent with
their actual meaning and the implementation - enc_data and plaintext
were swapped.
Also, the parameter names in the file aes_ccm.c were completely
different from the ones in the header. Since all functions in the
header file are consistent in their parameter naming, I chose to make
the implementation follow the header and not the other way around.
Signed-off-by: René Beckmann <rene.beckmann@grandcentrix.net>
This adds to the macros for device MMIO declaration so they can
be put into boot or pinned linker sections as needed.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This adds both boot and pinned sections to the linker
script for ia32. This is required for enabling demand
paging for kernel and data.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This allows interrupt service routine to be declared with
the __isr tag so they can be placed in the correct linker
section. The first would be putting them into the pinned
section.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This adds the necessary bits for linker scripts and source code
to specify which symbols need to be pinned in memory. This is
needed for demand paging as some functions and data must reside
in memory all the time and cannot be paged out (e.g. paging,
scheduler, and interrupt routines for functionality).
This is up to the arch/SoC/board to define the sections in
their linker scripts as the pinned section may need special
alignment which cannot be done in common script snippets.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This adds the necessary bits for linker scripts and source code
to specify which symbols are needed for boot process so they
can be grouped together.
One use of this is to group boot related code and data so these
won't interval with other kernel and application for better
caching.
This is a must for demand paging as some functions and data
must be available during the boot process and before the memory
manager is initialized. During this time, paging cannot be used
so symbols linked in virtual memory space are unavailable.
This is up to the arch/SoC/board to define the sections in
their linker scripts as section may need special alignment
which cannot be done in common script snippets.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
There is exactly one function being defined with TEXT_START
macro so the x86-32 __start can appear at the beginning of
text section. Since no one else is using it, better remove
TEXT_START to simplify things.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The generic version of SECTION_VAR() is adding an extra space
during expansion before second argument (e.g.
SECTION_VAR(section, variable) => ".section. variable"
instead of ".section.variable") which would result in build
error. So remove the "##" in macro to fix this, and now it
will also behave the same as SECTION_FUNC().
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This is similar to Z_GENERIC_SECTION() but the resulting
section name has a period as prefix. This eases the need
to create a section name macro for both assembly and C.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The cache API currently shipped in Zephyr is assuming that the cache
controller is always on-core thus managed at the arch level. This is not
always the case because many SoCs rely on external cache controllers as
a peripheral external to the core (for example PL310 cache controller
and the L2Cxxx family). In some cases you also want a single driver to
control a whole set of cache controllers.
Rework the cache code introducing support for external cache
controllers.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Remove this intrusive tracing feature in favor of the new object tracing
using the main tracing feature in zephyr. See #33603 for the new tracing
coverage for all objects.
This will allow for support in more tools and less reliance on GDB for
tracing objects.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Add Poll API and Work Poll tracing, default hooks, and documentation.
Signed-off-by: Torbjörn Leksell <torbjorn.leksell@percepio.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Adds generic trace hook macros for inserting trace hook for
function entry, exit, blocking, and object initialization
with a variable number of arguments (objects, return values,
etc.). Utilizing macro concatenation these macros produce
trace hooks of a similar format to the old trace system
with SYS_TRACING_OBJ_FUNC(k_thread, switched_in) being
turned into sys_trace_k_thread_switched_in() by the
preprocessor. Although these macros still rely on the manual
definition of each unique trace hook in tracing.h, the benefit
of not directly calling those is that we can enable/disable
trace hooks based on object type (k_thread, k_sem, etc.)
through the preprocessor while providing the ability of adding
type specific runtime trace processing similar to
SYS_TRACING_OBJ_INIT.
Signed-off-by: Torbjörn Leksell <torbjorn.leksell@percepio.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Several functions and macros have been replaced with new ones that
conform to current naming conventions, or provide more functionality,
mostly through using new representations for delayable work. Mark
these functions deprecated.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Avoid confusion with device runtime idle pm states and just use device
pm states.
This simplify the code a little bit and prepare the ground for having
a better definition of device pm states. Right now this code needed to
hijack two transitional states to not break the current code logic but
the goal is avoid it and have everything in one single place.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Device pm runtime was using semaphore to protect critical section but
enable / disable functions were waiting on the semaphore. So, just
replace it with a spin lock.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
The sync API was using k_poll_signal and in certain conditions is
possible multiple threads waiting on a signal leading to an undefined
behavior.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
The context parameter used across device power management is
actually the power state. Just use it and avoid a lot of
unnecessary casts.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Stack is aligned by 8 for 64 bit ISA and 4 for 32 bit ISA.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
Make variables where we store CPU registers values and
memory addresses bit agnostic.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
Mark the places where we intentionally use st instead of STR for
code common for ARCv2 and ARCv3.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
