In some case, we may need to describe a domain clock for a device
while there is no way to configure it (ex: USB clock set on PLL_Q output
on F405 devices > It is not selectable).
Then, configuring a device clock domain in the clock_control driver
will allow to retrieve its subsys rate.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Current divisor is 10000000 (should be 1000000).
For example, ESP32_CLK_CPU_240M / 10000000 == 24 MHz (incorrect).
Signed-off-by: Chris Wilson <christopher.david.wilson@gmail.com>
ESP32 and ESP32-S2 HW clock are tied to DTS clock configuration.
This changes updates the default configuration to retrieve
this information from DTS.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add support for Microchip MEC15xx to the XEC clock control driver.
MEC15xx 32KHz clock support uses the same 32KHz source for both the
PLL and peripherals. MEC152x does not include the PCR clock monitor
present in MEC172x. MEC15xx and MEC172x support internal silicon
oscillator, parallel and single ended crystal inputs, and the
32KHZ_PIN input. MEC152x supports fall back to internal silicon
OSC when VTR and 32KHZ_PIN are turned off. Therefore in MEC152x the
internal silicon oscillator can only be disabled if using an external
32KHz which is always on. For MEC152x the driver will only use the
PLL source clock device tree value.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Fix Microchip XEC clock control driver single-ended XTAL2 pin
initialization. Add support for external 32KHZ_IN pin as a
clock source including PINTRL to switch the GPIO to 32KHZ_IN
function. Add device tree option to disable internal silicon
oscillator if it is not required by the configuration. Add
device tree tuning options based on crystal and board layout.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
On STM32F1 series, configure USB(/OTGFS) prescaler based on DT.
When prescaler is set, PLL output clock is not divided.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The timer_ids contain timers that belong to any bus.
So, It should recognize with entire id, not only the CLOCK_ID_BIT part.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
DT_COMPAT_GET_ANY_STATUS_OKAY is not suited for the node's existing check.
(This macro returns the stem of the DTS macro name,
the stem part is not a defined symbol.)
Instead, it should use the DT_HAS_COMPAT_STATUS_OKAY macro.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
For the stm32 devices that have a HSI48 clock,
the driver enables it, like any other fixed clock,
if needed and supported by the serie.
For stm32L0, SYSCFG VREFINT is also required.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The stm32_clock_control_init is needed for implementation of custom
pm_state_exit_post_ops.
Signed-off-by: Artur Lipowski <Artur.Lipowski@hidglobal.com>
Routines called by users to release (and perhaps stop) the HFCLK
cannot synchronize with only the `hfclk_users` atomic variable,
because a thread can be preempted right after it clears the proper
bit in that variable but before the HFCLK is actually requested to
stop, and another user can then request the HFCLK to start. This can
result in HFCLK being stopped right after it was requested to start
and in `hfclk_users` holding an incorrect value.
Fix this by locking interrupts in those routines until the HFCLK is
stopped.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
The Flash latency depends on the sysclock
In case of the stm32F7 the regulator overdrive mode is set
depending on the sys clock freq.
The overdrive must be set before the first LL_SetFlashLatency.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
With the stm32U5, when the sysclock is > 55 MHz, the EPOD booster
must be configured before the PLL1 is enabled (see refMan).
This is the case when sysclock is on PLL1 sourced by MSIS or
HSE higher than 16MHz.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
In order to configure domain clock, clock_control_configure should be
used instead of clock_control_on which is only useful for bus clock gating.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Microchip MEC172x CPU and fast peripheral (QMSPI and PK) are
clock source is based upon an OTP setting. Add logic to adjust
clock source based on OTP value. If the OTP value is ever changed
this fix will allow calcluation of correct clock rate.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
clock_stm32_ll_common.h was missing <stdint.h> and <zephyr/device.h>. It
turns out things worked because <zephyr/init.h> has a forward
declaration of struct device.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Change automated searching for files using "IRQ_CONNECT()" API not
including <zephyr/irq.h>.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
mcux HAL pollutes namespace with stuff like ARRAY_SIZE, MIN, MAX, etc.
Luckily it only defines them if not already defined, so we can play with
include order to "fix" the problem. Move the infamous soc.h (which
includes HAL) after other Zephyr includes.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Some files using time_units.h API did not include it, e.g. for
sys_clock_hw_cycles_per_sec.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The sys* ops like sys_clear_bit are indirectly included via arch CPU
header. Other stuff like find_msb_set end up included via this header as
well.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Use the FSL_FEATURE_MCG_FFCLK_DIV define to decide if we should
call the api to get Fixed Frequency Clock.
This fixes Issue #49924
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
This adds a very basic driver to utilize the I3C IP block
on MCUX (e.g. RT685). Note that, for now, this only supports
being the active controller on the bus.
Origin: NXP MCUXpresso SDK
License: BSD 3-Clause
URL: https://github.com/zephyrproject-rtos/hal_nxp
Commit: 2302a1e94f5bc00ce59db4e249b688ad2e959f58
Purpose: Enabling the I3C controller on RT685.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
DT node "st,stm32f105-pll2-clock" already exists but was not actually used
and PLL2 was not being configured.
PLL2 is available on STM32F105/F107 and should be turned off after turning
off PLL and turned on before turning on PLL again since PLL2 can be
used as a source for PLL. Source for PLL2 is always HSE.
Signed-off-by: Pierre-Emmanuel Novac <piernov@piernov.org>
On some stm32 mcus, the LSE is enabled as system clock (LSESYS)
only when the LSEON and LSERDY are both set.
The bit LSESYSEN is set in the RCC BDCR register
and the driver is waiting for the LSESYSRDY to be set.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add R-Car Gen3 PWM driver.
Clock diviser is automatically adjusted according to requested period
and duty-cycle in order to obtain as much accuracy as possible.
Indeed, in order to improve PWM accurancy, the PWM clock has to fit
the requested period. So use the given period_cycle to define if the
clock as to be adapted. In such case, increase/decrease the clock
diviser to adapt the period_cycle and be sure that it fits into the
10 bits counter of the PWM controller.
Tested on H3ULCB on pwm0 and pwm4.
Signed-off-by: Pierre Marzin <pierre.marzin@iot.bzh>
MCO1 is also available on STM32F1 series (on top of STM32F4), allow
selection of MCO1 source with CLOCK_STM32_MCO1_SRC_* Kconfig parameters.
Available MCO1 sources are slightly different between STM32F4
(LSE, HSE, HSI, PLLCLK) and STM32F103 (HSE, HSI, PLLCLK/2, SYSCLK), and
STM32F105/F107 have a few more (EXT_HSE, PLL2CLK, PLLI2SCLK, PLLI2SCLK/2).
MCO1 on STM32F1 does not have a configurable divider (unlike STM32F4),
HAL call only configures source.
STM32F1 do not have MCO2.
Signed-off-by: Pierre-Emmanuel Novac <piernov@piernov.org>
This patch adds a clock control driver for GD32 platforms. It is
important to note that the driver is only able to handle peripheral
clocks, but not "system clocks" (e.g. PLL settings, SYS_CK, etc.). On
some similar platforms (STM32) this task is embedded in the same clock
driver, performed at init time but with no options to do any
manipulation at runtime via the API calls. The clock control API as-is
is really orthogonal to "system clocks", and it is arguably a bad idea
to embed system clock init code in a clock control driver. It can be
done at SoC level still using Devicetree as a source of hardware
description/initial configuration.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
soc.h has been removed for ARM64 SoC platforms and it is also needed by
ARM32, so remove it from related drivers.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Add device specific clock initialization, which uses
reset reason cause information to proper define
peripherals clock state.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
prev_temperature was only used if USE_TEMP_SENSOR is true. Make its
definition conditional.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The temperature sensor was only needed when
CONFIG_CLOCK_CONTROL_NRF_CALIBRATION_MAX_SKIP > 0. Implementation did
not reflect this dependency correctly, and sensor sampling code was
always compiled. Also removed CONFIG_MULTITHREADING checks, since this
driver is only compiled if CONFIG_MULTITHREADING=y.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
ASSERT was failing when `r8a7795_cpg_mssr_start_stop` was
called for a "core" clock.
This ASSERT statement and "mstpcr" table of registers are
only meant to be used when starting or stopping a "module" clock.
Moved ASSERT statement to `rcar_cpg_mstp_clock_endisable`
as well as "reg" & "bit" calculation.
Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
