It was being included twice. Now it's included once. CI requires a commit
description.
Signed-off-by: Armin Brauns <armin.brauns@embedded-solutions.at>
Without this, setting a value of 0 leaves the bits unchanged rather than
zeroing them.
Signed-off-by: Armin Brauns <armin.brauns@embedded-solutions.at>
Added a new watchdog driver which can handle a multiple wdt_dw instances
and can control the pause signal.
The mlt platform has three designware watchdogs, one for each core.
I decided to create a separate intel watchdog driver for the following
reasons:
1. All three devices share the same interrupt number. Each watchdog reports
an interrupt to the core to which it has been assigned. The same interrupt
number cannot be used by multiple devices in the device tree. So, it would
be assigned to only one device. The other dw watchdog devices would use
this assignment, even though it would not be described for them in the dt.
The interrupt handler function in dw watchdog checks the interrupt flag.
If the interrupt was connected to the first watchdog, and the second or
third watchdog signal an interrupt, the interrupt handler of the first
device would ignore it because it would not have set the interrupt flag.
The watchdog device don't knows anything about the existence of the others
devices.
2. The designware watchdog only supports a hardware pause signal. It cannot
be paused programmatically. On the mtl platform, there is a separate group
of control registers for all per-core watchdogs. There are GPIO-like
registers that allows control of a hardware pause signal for subordinate
watchdogs. This separate block is shared by all three watchdogs.
3. The base addresses of the subordinate watchdogs are read from the
aforementioned control registers. As a result, in the device tree we have
only one base address for the intel watchdog, which points to the pause
control registers and containing the base addresses of the subordinate
devices.
Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
The cadence i3c ip requires it's retaining registers to be updated
when a device is detached or attached.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
There are some needs to attach and reattach i3c/i2c devices at runtime
Some I2C devices can have special registers where the address can be
changed at runtime. Also some I3C devices can be powered off at runtime
freeing up the address space they take up. These new APIs allow for these
to be changed at runtime. This also moves some config/data in to a common
i3c config/data structure which would allow the api to operate on to be
common for all I3C drivers.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
This adds the reattach api necessary for writing the i3c retaining
registers within the cdns i3c when the dynamic address changes.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
Some I3C controllers have retaining registers which are used to contain
the DA of the i3c device. This needs to be updated every time the DA is
updated with SETNEWDA or SETDASA
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
Reading the UID_BASE_ADDRESS requires disabling the icache
of the stm32h5x mcu.
Else a bus fault error occurs reading Address: 0x8fff800-0x8fff808
Enable afterwards.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add a driver that listens for input events and reports them on a kscan
API. This allows porting kscan drivers to the input APIs while
maintaining compatibility with the existing kscan based applications.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
This macro just uses an existing cache API and is not widely being used.
Use the API directly which will be changed to use a public cache API in
a later commit.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Replace pointer construction macro with value from config struct.
Fixes what appears to be an oversight from #55522.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
When releasing a paused stream, clearing MIC_MUTE bit is necessary.
Without unmuting there will be no input data after resume.
Signed-off-by: Fred Oh <fred.oh@linux.intel.com>
Clearing SOFT_RESET bit applies to ACE as well. In case of ACE,
this should be done before setting start bits for CIC and FIR.
Signed-off-by: Fred Oh <fred.oh@linux.intel.com>
Introduce flash extended operations that can be used to disable access
to option and control registers until reset. Disabling access to these
registers improves system security, because flash content (or protection
settings) can't be changed even when exploit was found.
On STM32 devices, registers can be locked until reset by writing wrong
key during unlock procedure. It triggers a bus fault, so during the
procedure we need to ignore faults and clear bus fault pending bit.
Please note that option register disabling was implemented for devices
that have OPTCR register (F2, F4, F7 and H7). Implementation on other
devices requires more testing, since documentation is not precise
enough. Disabling control register was implemented for devices that
have CR register.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
This patch makes possible to choose custom byte which should be used
to enable non-permanent readout protection (RDP1). Actually, any byte
except 0xAA and 0xCC (which are used by RDP0 and RDP2 respectively)
can be used to enable RDP1 but in multi-image environment, some other
image could check if RDP1 is enabled by comparing it to some hardcoded
value.
If property is not defined, 0x55 will be used to enable RDP1. The
default value comes from STM32 HAL.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
This patch adds flash readout protection support for STM32F4 devices
family. These devices can enable protection on entire flash content.
Readout protection functionality was exposed as vendor extended
operation. To change readout protection state, caller should provide a
structure which describes desired RDP state.
Enabling readout protection permanently or disabling readout protection
(changing from level 1 to level 0) is guarded by
CONFIG_FLASH_STM32_READOUT_PROTECTION_PERMANENT_ALLOW and
CONFIG_FLASH_STM32_READOUT_PROTECTION_DISABLE_ALLOW respectively.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
This patch adds sector write protection support for STM32F4 devices
family. These devices can protect flash content with sector precision.
Write protection functionality was exposed as vendor extended operation.
To change write protection state, caller should provide mask of enabled
and disabled sectors.
Function responsible for locking/unlocking option bytes was implemented
for all STM32 devices supported by this driver.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Introduce the stm32h5 serie to the the existing flash driver
It is based on the stm32l5 model.
Add a function to check if the flash is in dual
or single bank mode.
Some stm32 devices can map 2 or 1 flash banks.
Adapt the FLASH register names for the stm32h5 mcu.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add the driver for the clock control of the new stm32h5.
See the corresponding Ref Man to get the clock scheme :
HSI, CSI, HSI48, HSE, LSE, and 2 or 3 PLLs
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Unify the drivers/*/Kconfig menuconfig title strings to the format
"<class> [(acronym)] [bus] drivers".
Including both the full name of the driver class and an acronym makes
menuconfig more user friendly as some of the acronyms are less well-known
than others. It also improves Kconfig search, both via menuconfig and via
the generated Kconfig documentation.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
- That MIN_DELAY is a magic arbitrary number that is never going to be
right for all cases. Get rid of it in favor of a smarter solution.
- `sys_clock_set_timeout()` should not base its next match value on the
current time. Tracking the `last_tick` and `last_elapsed` values avoids
the need for all the tick rounding computation.
- Clamp the next timeout to HPET_MAX_TICKS/2. This leaves room for the
added elapsed time and any possible IRQ servicing delay.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Fix port array definition in kinetis pinctrl driver
so that it handles more flexibly the cases where the
number of PORT peripherals is more than 3, rather than only
handling the case where there are 5.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
After enabling the ADC, the peripheral has a certain delay (about 1ms)
to set its ADC Ready flag in the ADC ISR register.
In between, the ADRDY is still 0 and the ADEN is 1 in the CR.
The ADC can be used for conversion, only when the ADRDY bit is set
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add missing guard which prevents use of nrf_rtc_timer on
the same RTC instance (RTC1) as counter driver instance.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Add binding and sensor attribute to allow single phase
mode where only one signal is required from the encoder.
The signal must be connected to Phase A input.
Signed-off-by: Jeppe Odgaard <jeppe.odgaard@prevas.dk>
Add config and data structs to the vnd,gpio test driver as these are
required by the GPIO API.
Fixes: #55884
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Add documentation for the update_sampling_pnt() function and rename a few
internal variables to improve readability.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Respect the range limits of phase_seg1 when attempting to distribute ts1
between prop_seg and phase_seg1.
Even distribution may not be possible if the allowed ranges of prop_seg and
phase_seg1 are not equal.
Fixes: #55919
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Microchip XEC ADC and ADC V2 driver were merged into one
That PR did not change the ADC API test and ADC shell resulting
in twister build failures. Fixed both ADC API test and ADC shell.
Signed-off-by: scott worley <scott.worley@microchip.com>
Devicetree local-mac-address and zephyr,random-mac-address support added.
Updated w5500_set_config() to support ETHERNET_CONFIG_TYPE_MAC_ADDRESS
and change the MAC address at runtime.
Signed-off-by: Rainer Paat <rapaat@gmail.com>
The number of available EasyDMA MAXCNT bits is now defined per-instance
in Devicetree.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
temporary_table is a trivial copy of virtual_memory_regions, it isn't
clear why it's needed. All the more that it's freely mixed with
virtual_memory_regions itself. Also change a variable name to avoid
confusion and improve indentation.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
update espi_vwire_signal enum to refer all platform specific
usage virtual wires to ESPI_VWIRE_SIGNAL_SLV_GPIO_x
Virtual wires used for USB-C port over current (OCB)
have been defined as macros mapped to the corresponding
espi_vwire_signal enum
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Change device tree VW routing to a form allowing overrides.
Add two new DT optional properties for specifying the reset
source and reset value of each virtual wire. Only virtual
wires that are enabled using the status property are modified.
NOTE: eSPI virtual wires are controlled in groups of 4 by
hardware. The optional reset signal source properties applies
to all four virtual wires in the group. If this field is
changed from the hardware default, it should be changed for
only one virtual wire in the group. If the property exists
in more than one wire in the group it must be set to the
same value.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Modify Mircrochip MEC172x eSPI driver to get eSPI virtual wire
hardware routing from device tree.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
The clock control driver requires three pieces of information:
PCR register index, bit position, and clock domain. Clock domain
was missing from DT information and MCHP macros.
Signed-off-by: Manimaran A <manimaran.a@microchip.com>
Deleted adc_mchp_xec.c and microchip,xec-adc.yaml file.
DTSI, yaml, CMakeLists.txt and Kconfig.xec files are
updated for compatible.
Signed-off-by: Manimaran A <manimaran.a@microchip.com>
Updated the "adc_mchp_xec_v2.c" adc driver to support both MEC172x and
MEC15xx SOC.
ADC smapling clock configuration updated using DTS.
Signed-off-by: Manimaran A <manimaran.a@microchip.com>
