Commit Graph

12 Commits

Author SHA1 Message Date
Alberto Escolar Piedras
196341c18b samples: Switch integration_platforms from native_posix to native_sim
For all remaining samples which now set their integration platform
as native_posix(_64) switch them to native_sim(_64)

Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
2023-11-20 12:02:48 +01:00
Tom Burdick
36d8c1b7f7 samples: Remove platform filters for external_lib
Instead prefer to add the tag to ignored tags in the board yaml
where its clearer for both cavs25 and other cavs/ace boards what
to ignore even if duplicated.

Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
2023-01-10 18:29:35 -05:00
Andy Ross
3d81464194 tests: samples: Add targetted platform_excludes for intel_adsp_cavs15
This platform has a tiny handful of remaining tests that fail.  We
will track them as issues, but let's exclude them from integration
testing to allow full runs to complete.  Often a hung device in one
test will break an entire twister run.

Tests with known (and tracked) failures:

  samples/application_development/external_lib
  samples/posix/eventfd
  samples/userspace/hello_world_user
  tests/kernel/fatal/message_capture
  tests/net/socket/socketpair
  tests/portability/cmsis_rtos_v2

These tests never fail in isolated testing, but are reliable timeouts
when run in sequence in a big twister run.  It's possible that the bug
here may be in twister or the flash/serial scripts:

  tests/crypto/tinycrypt
  tests/subsys/logging/log_immediate
  tests/subsys/logging/log_output

See: #32836

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2021-03-08 19:25:25 -05:00
Kumar Gala
59fd4bfdfd samples: app_dev: set integration_platforms to native_posix
Set integration_platforms on these samples to just native_posix.  This
should be sufficient to make sure these tests build and run.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2021-03-03 09:11:53 -06:00
Daniel Leung
b7eb04b300 x86: consolidate x86_64 architecture, SoC and boards
There are two set of code supporting x86_64: x86_64 using x32 ABI,
and x86 long mode, and this consolidates both into one x86_64
architecture and SoC supporting truly 64-bit mode.

() Removes the x86_64:x32 architecture and SoC, and replaces
   them with the existing x86 long mode arch and SoC.
() Replace qemu_x86_64 with qemu_x86_long as qemu_x86_64.
() Updates samples and tests to remove reference to
   qemu_x86_long.
() Renames CONFIG_X86_LONGMODE to CONFIG_X86_64.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2019-10-25 17:57:55 -04:00
Anas Nashif
da5f185e06 samples: add test identifier
Add unique identifier instead of just 'test' for samples.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2019-03-29 17:44:11 -04:00
Andy Ross
b69d0da82d arch/x86_64: New architecture added
This patch adds a x86_64 architecture and qemu_x86_64 board to Zephyr.
Only the basic architecture support needed to run 64 bit code is
added; no drivers are added, though a low-level console exists and is
wired to printk().

The support is built on top of a "X86 underkernel" layer, which can be
built in isolation as a unit test on a Linux host.

Limitations:

+ Right now the SDK lacks an x86_64 toolchain.  The build will fall
  back to a host toolchain if it finds no cross compiler defined,
  which is tested to work on gcc 8.2.1 right now.

+ No x87/SSE/AVX usage is allowed.  This is a stronger limitation than
  other architectures where the instructions work from one thread even
  if the context switch code doesn't support it.  We are passing
  -no-sse to prevent gcc from automatically generating SSE
  instructions for non-floating-point purposes, which has the side
  effect of changing the ABI.  Future work to handle the FPU registers
  will need to be combined with an "application" ABI distinct from the
  kernel one (or just to require USERSPACE).

+ Paging is enabled (it has to be in long mode), but is a 1:1 mapping
  of all memory.  No MMU/USERSPACE support yet.

+ We are building with -mno-red-zone for stack size reasons, but this
  is a valuable optimization.  Enabling it requires automatic stack
  switching, which requires a TSS, which means it has to happen after
  MMU support.

+ The OS runs in 64 bit mode, but for compatibility reasons is
  compiled to the 32 bit "X32" ABI.  So while the full 64 bit
  registers and instruction set are available, C pointers are 32 bits
  long and Zephyr is constrained to run in the bottom 4G of memory.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2019-01-11 15:18:52 -05:00
Anas Nashif
4843c69f06 sample: external_lib: support console harness
Evaluate console output of sample.

Enable on other platforms, this should not be whitelisted.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-01-25 04:45:35 +05:30
Anas Nashif
eba1bbd705 samples: remove more build_only tags
Remove build_only and add harness type needed for the sample/test to
allow running with sanitycheck and on devices once we have harness
support.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-12-28 20:24:29 -05:00
Anas Nashif
23f81eeb42 tests/samples: fixed yaml syntax
Use a map directory, avoid the list which makes parsing a bit
cumbersome.

Fixes #5109

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-12-11 14:47:08 -05:00
Anas Nashif
0356590df5 tests: samples: fix yaml syntax
Fix indentation and syntax and make it pass yamllint tool.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-10-15 08:15:00 -04:00
Anas Nashif
cc24f4b03c tests: samples: convert testcase files to yaml
This will prepare test cases and samples with metadata and information
that will be consumed by the sanitycheck script which will be changed to
parse YAML files instead of ini.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-06-21 20:56:53 -04:00