This commit catch the return code of the spi_config function and
early returns on error so that high level spi transfer api gets
the error too.
Signed-off-by: Adrien MARTIN <adrienmar@kickmaker.net>
fixes an incorrect dma configuration. When lpc dma driver was extended
with gather/scatter support the spi dma driver stopped working.
Signed-off-by: Johan Carlsson <johan.carlsson@teenage.engineering>
Removed PM device runtime support from drivers in PD_SYS domain.
Update the rest device drivers to call pm_device_runtime_get/put()
functions when CONFIG_PM_DEVICE_RUNTIME is enabled.
Signed-off-by: Ioannis Damigos <ioannis.damigos.uj@renesas.com>
This driver could end up doing a great deal of work inside the ISR when
large SPI transfers were in use, which could cause significant IRQ
latency. For the normal, non-async SPI transfer case, use events to
signal the calling thread to complete the work rather than performing
FIFO transfers inside the ISR.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
Add an optional DT property to specify the size of the RX/TX FIFO
implemented within the SPI core. The property name used is the same one
used by Xilinx's device tree generator.
When the FIFO is known to exist, we can use the RX FIFO occupancy register
to determine how many words can be read from the RX FIFO without checking
the RX FIFO empty flag after every read. Likewise with the TX FIFO, we can
use the FIFO size to avoid checking the FIFO full flag after every write.
This can increase overall throughput.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
Add support for a workaround required when using the Xilinx Quad SPI core
with the USE_STARTUP option, which routes the core's SPI clock to the
FPGA's dedicated CCLK pin rather than a normal I/O pin. This is typically
used when interfacing with the same SPI flash device used for FPGA
configuration. In this mode, the SPI core cannot actually take control
of the CCLK pin until a few clock cycles are issued, which would break
the first transfer issued by the core. This workaround applies a dummy
command to the connected device to ensure that the clock signal is in the
correct state for subsequent commands.
See Xilinx answer record at:
https://support.xilinx.com/s/article/52626?language=en_US
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
This commit should deal with adding support
for asynchronous operations. It also adds
support for DMA acceleration via a Kconfig
variable (enaled by default as DMA should
be considered scales faster than the
interrupt-driven approach).
Signed-off-by: Ioannis Karachalios <ioannis.karachalios.px@renesas.com>
I/O Devices were meant to be handles of sorts and had a built in mpsc queue
as this made sense initially. As time has gone on it turned out that often
we wanted the mpsc queue to be an implementation detail hidden in a driver.
In fact pretty much all drivers work this way now.
Keeping the struct mpsc queue as a member of rtio_iodev meant wasted memory
in cases where it wasn't used. It also meant a bit of confusion as the
queue might be accidently used in places where it shouldn't be.
Remove the mpsc queue member from struct rtio_iodev and the last remaining
usages of it. Will ensure RTIO for 3.7 LTS avoids causing unneeded churn
for future users.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
This commit adds support for configuring SPI frequency per transaction.
The "clock-frequency" devicetree property is used as the default
frequency unless the peripheral being communicated with has a lower
"max-spi-frequency" (passed to the driver as spi_config::frequency).
An error is returned if the requested frequency is higher than the
hardware can support. This limit is half the peripheral clock (PCLK on
Series 2, HFPERCLK on Series 0/1) for SPI in controller mode.
Previously, the driver hard-coded 1 MHz operation. For backwards
compatibility, default to 1 MHz if the "clock-frequency" property is not
set in devicetree.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
This commit adds support for devices such as EFR32xG24 in the SPI
driver, as these devices only have a single USART peripheral.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
The clock should be initialised only once at the
drivers init function.
Check wether the subsys needs to be disabled in
peripheral initialization according to reset reason
in clock control.
Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
Moves the rtio_ prefixed lockfree queues to sys alongside existing
mpsc/spsc pbuf, ringbuf, and similar queue-like data structures.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
SPIM12x instances can perform DMA only from memory region
that is cacheable by default.
SPIM12x instances pins are configured via CTRLSEL mechanism,
which prevents the GPIO registers from ensuring correct bus
state when peripheral does not drive the bus lines.
External configuration of SPIM12x ENABLE register fixes this issue.
Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
Chip Select signal must be deactivated only after transaction
is finalized. In async case this means it cannot be done from
`transceive` call context, as this context is left as soon as
transfer is initialized.
Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
This commit adds support for the SPI which
can be found in Apollo3 SoCs, it can work in
both DMA and non-DMA modes
Signed-off-by: Hao Luo <hluo@ambiq.com>
Code adds pm action function that stores SPI configuration
before PD_COM is allowed to be turned off.
PM_DEVICE_RUNTIME scheme is also supported
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Namespaced the generated headers with `zephyr` to prevent
potential conflict with other headers.
Introduce a temporary Kconfig `LEGACY_GENERATED_INCLUDE_PATH`
that is enabled by default. This allows the developers to
continue the use of the old include paths for the time being
until it is deprecated and eventually removed. The Kconfig will
generate a build-time warning message, similar to the
`CONFIG_TIMER_RANDOM_GENERATOR`.
Updated the includes path of in-tree sources accordingly.
Most of the changes here are scripted, check the PR for more
info.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Fix timing in SPI bitbang driver.
The issue occurs with CPHA=1 when the input data is changed immediately
after the clock shift on the last bit of the read.
Because we read the input bit after changing the clock, this bit
becomes invalid.
Instead of doing wait, clock-change, read. Do wait, read, clock-change.
Signed-off-by: Joakim Andersson <joerchan@gmail.com>
Some Ambiq Apollox Blue SOC (e.g. Apollo3 Blue) uses internal designed
BLEIF module which is different from the general IOM module for SPI
transceiver. The called HAL API will also be independent. This driver is
implemented for the BLEIF module usage scenarios.
Signed-off-by: Aaron Ye <aye@ambiq.com>
Subghzspi instances cannot have any pinctrl configs. This causes a
failure of the power management suspend and resume operations for the
subghzspi instance because no "default" pinctrl is found.
Fix that by skipping the pinctrl parts on subghzspi instances.
At the same time fix a copy and paste in the suspend error message.
Fixes: b567a7db83
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Add runtime power management suppor to the STM32 SPI driver. This allows
the driver to be suspended when not in use, and as a stop effect removes
the need to suspend/resume around each transition to stop mode.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
The Synopsys Designware SPI peripheral exists in two versions with
slightly different register layouts. Added a Kconfig option that makes the
driver compatible with the HSSI register layout.
Signed-off-by: Rafał Kuźnia <rafal.kuznia@nordicsemi.no>
Align the SPI init priority with other devices.
Other bus-devices like UART and I2C are init at standard kernel
device level (50), but SPI is at 70 and there appears to not be
a reason for it.
GPIO is init at 40 so there should not be an issue to use the default.
Signed-off-by: Joakim Andersson <joerchan@gmail.com>
Add support for half-duplex (3-wire) SPI operation using the Raspberry
Pi Pico PIO. To allow control of the size of the driver, including
half-duplex support is optional, under the control of Kconfig options.
The original PIO source code is also included as a reference.
Corrected 3-wire tx/rx counts.
Enable half-duplex code based on DTS configuration
Replace runtime checks with static BUILD_ASSERT()
Remove too-fussy Kconfig options
Removed PIO source per review request
Signed-off-by: Steve Boylan <stephen.boylan@beechwoods.com>
Redundant kLPSPI_MasterPcsContinuous transfer config flag
is eliminated since this is set earlier.
Signed-off-by: Dipak Shetty <dipak.shetty@zeiss.com>
Previously the logic was inverted for error_callback_en where 0 was
enablement and 1 was disable. This was likely done so that the default,
sensibly so, was to enable the error callback if possible. A variety of
in tree users had confused the enable/disable value.
Change the name of the flag to error_callback_dis where the default
remains 0 (do not disable the callback!) and correct in tree uses of the
flag where it seemed incorrect.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
LPFlexcomm is a MFD device hence select this Kconfig whenever
it is enabled.
Remove the selection from the individual driver Kconfig files.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
The Low Power Flexcomm driver manages the interrupt handling
and provides an API to register interrupt callbacks.
Register the NXP LPSPI interrupt handler.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Update the driver to account for variations in the SDK driver
when it uses the instance number instead of the base address.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Keep the SPI enabled when performing multiple transaction with
SPI_HOLD_ON_CS.
In such case, the end of transaction is marked by application calling
spi_release.
Signed-off-by: Michele Sardo <msmttchr@gmail.com>
