Setting the number of memory wait cycles must take place while the clock
is set to 32MHz or less. This patch ensure the MEMWAIT register is
changed before the clock is changed from its default value (of 8MHz).
Note that in order to set MEMWAIT to 1 the power control mode must be
set to high speed (which is why the lines of code interacting with the
OPCCR register have also been moved).
Signed-off-by: Ian Morris <ian.d.morris@outlook.com>
Remove address-of operator ('&') when assigning `clock_control_xxx_init`
function pointer in `DEVICE_DT_INST_DEFINE` macro.
This change aims to maintain consistency among the drivers in
`drivers/clock_control`, ensuring that all function pointer assignments
follow the same pattern.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
There was an error in calculation of LFXO INTCAP code that prevented
obtaining desired XTAL accuracy below 50PPM. The error was fixed
the accuracy should be within expected range.
Signed-off-by: Piotr Pryga <piotr.pryga@nordicsemi.no>
Smartbodn does not have dedicated USB clock.
For USB to work PLL needs to be turned on.
To allow for flexible configuration artificial USB clock
is added that can be operated via clock_control subsystem.
This new clock turns on PLL when USB subsystem is enabled.
PLL can also be request in DT if application requires
more speed.
PLL can be automatically turned off when USB enters suspend
state and application did not requested it.
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Adds get_status API for clock_stm32_ll_u5 driver
Signed-off-by: Adam Berlinger <adam.berlinger@st.com>
Signed-off-by: Abderrahmane Jarmouni <abderrahmane.jarmouni-ext@st.com>
The clock should be initialised only once at the
drivers init function.
Check wether the subsys needs to be disabled in
peripheral initialization according to reset reason
in clock control.
Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
Found via static analysis. Two separate error paths where failing to
check the return code leads to undefined behavior:
1. In `litex_clk_get_phase`, the divider stays set to 0 when
`litex_clk_get_clkout_divider` errors out, which leads to a division
by 0.
2. In `litex_clk_calc_duty_normal`, the `duty` struct is used
uninitialized if `litex_clk_get_duty_cycle` errors out.
In both case, checking the return code and returning early resolves the
issue.
Signed-off-by: François Baldassari <francois@memfault.com>
Add ENET_1G clock value to the RT11XX CCM version.
Implemented enabling ENET_1G clock and getting its frequency.
Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com>
Introduce the stm32h7RS serie to the clock_controller,
based on the stm32h7 clock driver
Datasheet DS14359 rev 1 gives CPU max freq of 500MHz
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Default the clock accuracy for the simulated 54L15 target
just as for the real target.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Fix a compilation error occurring when a prescaler was set for ADC on F1
and F3 family.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
This commit should deal with the followings:
1. PLL requires that VDD level be changed to 1V2 and then released
to 0V9 when it's turned off. Changing the VDD level should be
done when the regulator driver is available. Otherwise, the VDD
level will be fixed to 1V2 (reset value).
2. Check if PLL is allowed to be turned off as it might happen that
USB is enabled which is clocked by PLL.
3. Do not wait for the PLL to lock. This is now performed silently
when PLL is requested.
4. Before switching to PLL we should check if PLL is already enabled
as it might happen that PLL node is initially disabled.
Signed-off-by: Ioannis Karachalios <ioannis.karachalios.px@renesas.com>
This patch adds a timeout to the clock_control_on() implementation. The
reason for this timeout is to prevent system freezes when the PLL is
configured incorrectly, or, if BICR is wrong. The locking time of the
AUXPLL is <30us, however, when it starts it also starts other
dependencies which take much longer to become ready. The locking time
has been experimentally measured to be around 2ms, so a 10x bound has
been added.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
This WDT is responsible for monitoring the external
32.728 Hz crystal connected to pins XTAL_32K_P and
XTAL_32K_N. If an oscillation failure is detected
the hardware automatically switch to RTC_RC_SLOW
clock source and triggers an interrupt.
Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
STM32 MCU shall set voltage regulator level with respect to set clock
frequency to reach optimal power consumption.
Voltage regulator is set prior to clock setting based on configuration
from dts/overlay file. Config_regulator_voltage is set as weak in
clock_stm32_ll_common - config_regulator_voltage can be
extended to other STM32 families without need to rewrite heavily
family clock driver, default one can be still used.
Signed-off-by: Lubos Koudelka <lubos.koudelka@st.com>
Add a new driver for the AUXPLL peripheral found in some new Nordic
SoCs, e.g. nRF54H20. AUXPLL is used to clock some peripherals like e.g.
CAN. Note that driver is implemented natively as Nordic HAL lacks
definitions for the AUXPLL IP, this may be changed once these become
available.
Note that usage of nrf_auxpll_config_set generates unnecessary extra
assembly code compared to the proposed API in
https://github.com/zephyrproject-rtos/hal_nordic/pull/185 which
guarantees static initialization and single write access, possible in
the Zephyr context. However, current solution has been enforced until
further discussion on raw access APIs takes place.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
This commit removes unnecessary initialization of the local variable
where its value is guaranteed to be overwritten by subsequent operations.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Use a code spell-checking tool to scan and correct spelling errors in
the following files:
- clock_stm32_ll_common.c
- clock_stm32_ll_h5.c
- clock_stm32_ll_h7.c
- clock_stm32_ll_u5.c
- clock_stm32_ll_wba.c
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Clock must be restored as soon as the SoC leaves standby.
Keep the logic inside the SoC instead of delegate it to the pm
subsystem.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
The RTC subsystem in espressif's SOCs, among other tasks
is responsible for clock selection for CPU and for low
power domain clocks such as RTC_SLOW and RTC_FAST.
This commit allows for proper clock source and rate
selection for CPU, using the espressif,riscv and
espressif,xtensa-lx6/7 bindings.
It also enables clock selection for RTC_FAST and RTC_SLOW,
that impacts some peripherals, such as rtc_timer.
Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
- Add initial version of CYW920829M2EVK-02 board
- [drivers: clock_control] Make it possible to set up both iho and imo
clocks instead of just one or the other
Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
The CMAC uses lp_clk as a sleep clock so it has to be updated if
frequency of lp_clk has changed. This happens either after XTAL32K
settling or RCX calibration.
Signed-off-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
1. Update the clock control driver so it can update timing settings for
QSPIC2 following system clock transitions (translated based on
AHB AMBA bus clock).
2. Remove the QSPIC related subroutines and use the respective HAL API
which is now available.
3. Add support for PM (CONFIG_PM_DEVICE). This is required as QSPIC2
register file is powered by PD_SYS which is turned off during device
sleep and so registers contents are lost (in contrast to QSPIC which
is used to drive the flash memory).
Signed-off-by: Ioannis Karachalios <ioannis.karachalios.px@renesas.com>
Added initial board support for the
frdm_ke15z board.
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
Signed-off-by: Pavel Krenek <pavel.krenek@nxp.com>
RC32K and RCX low power clocks require runtime calibration to work
correctly.
Frequency of those clock can differ from chip to chip, one constant
value from Kconfig may not be best when low power clock (sourced
from RCX or RC32K) is used for system tick.
This code modifies global z_clock_hw_cycles_per_sec variable that
is used when TIMER_READS_ITS_FREQUENCY_AT_RUNTIME is enabled
in Kconfig.
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
1. The only valid values of MCLKD clock frequency
are between 40Mhz to 50Mhz.
2. If DMA is used, the APB4_CLK clock frequency must
be equal to or higher than 20Mhz.
Signed-off-by: Alvis Sun <yfsun@nuvoton.com>
We are not able to achive 50ppm on nRF54L.
Working on fixing it propperly, but untill we do set what we get.
Signed-off-by: Martin Tverdal <martin.tverdal@nordicsemi.no>
The lpadc driver needs to obtain its functional clock to configure
the acquisition time. This patch add support for I.MX RT three digit
parts, I.MX RT11xx parts, and LPC parts.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
- update the console configuration defines references
- add missing header file with flash capabilities
- replace all console wait-until-ready calls by single one
Signed-off-by: Marek Matej <marek.matej@espressif.com>
