The nmi_on_reset.S functions are used by all ARM platforms. It
makes no sense to repeat the same code for all platforms. Moving
the code from each SOC implementation to arch/arm/core.
The same treatment for the NMI_INIT() macro. Moving it from a per
SOC implementation to the include/arch/arm/cortex_m/nmi.h.
Change-Id: I574d8880a44046cc7b9e1b635e80d6e83657b8c1
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
The app-facing interface for configuring interrupts was never
formally defined, instead it was defined separately for each arch
in their respective arch-specific header files. Occasionally these
would go out of sync.
Now there is a single irq.h header which defines this interface.
To avoid runtime overhead, these map to _arch_* implementations of
each that must be defined in headers pulled in by arch/cpu.h.
Change-Id: I69afbeff31fd07f981b5b291f3c427296b00a4ef
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
We have a new policy: users should not be able to configure
an interrupt with "forbidden" priority levels, and any priority
levels with special semantics will be activated by flags.
Change-Id: I757c19cfedcb1d0938eaf4da348ddafb71b3e001
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
It's not a function and requires all its arguments to be build-time
constants. Make this more obvious to the end user to ease confusion.
Change-Id: I64107cf4d9db9f0e853026ce78e477060570fe6f
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Add sys_exc_connect() (and its x86-compatible alias nanoCpuExcConnect())
that allows connecting an exception handler at runtime.
The current implementation is a bit of a bastard, to avoid disturbing
the current implementation of the exception handlers. Instead of hooking
_exc_wrapper() in all vectors and adapting the exception handlers, the
current exception handlers are still hooked directly in the vectors.
When an exception is hooked at runtime, _exc_wrapper() gets installed in
the vector and the real handler gets inserted in _sw_exc_table; this
means that the scheme only works with non-XIP kernels.
This should be enhanced so that _exc_wrapper() is hooked in all vectors,
and that current exception handlers (for faults mostly) are reworked to
be inserted in the _sw_exc_table and wrapped in _exc_wrapper().
Change-Id: Icaa14f4835b57873d2905b7fbcbb94eeb3b247d1
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Rename the function and allow it to handle the 'type'
argument, which is ignored in this case.
Change-Id: I3d3493bea4511b2d026747505e7e52c5acc85012
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
The ESF was built using the 'alias' names of the GPRs (a1, lr, pc, etc)
rather than their 'real' name (rN).
Change-Id: I49cae5e94869a79a3165dc7f2347d8cec39dbf67
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
On ARM, GPRs are often known by two names. E.g. the stack pointer is
both 'sp' and 'r13', the first parameter to a function 'a1' and 'r0',
etc. This macro allows defining them in a data structure, e.g. in the
ESF, without having to create a union, use the correct type, etc: it is
less error-prone and makes for shorter code.
sys_define_gpr_with_alias(name1, name2)
Change-Id: Ie4a6caa1ac23f26be4f7f0e05e9265f2655062cc
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
The image will be linked at a different address and with different
ROM/RAM sizes to allow running a bootloder image that loads a payload
image. The addresses/sizes depend on if it is a XIP image or not
(CONFIG_XIP), and in the case of a XIP image, if it is a bootloader
image (CONFIG_IS_BOOTLOADER) or not.
In the case of a bootloader, it is given the full ROM and
CONFIG_BOOTLOADER_SRAM_SIZE kB of SRAM. When not a XIP image, it is given
the full SRAM minus CONFIG_BOOTLOADER_SRAM_SIZE kB, and is linked at the
start of SRAM.
Change-Id: Ibbb693c7bff022f313dac40f21c04a61f4bed115
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Adds C++ support to the build system.
Change-Id: Ice1e57a13598e7a48b0bf3298fc318f4ce012ee6
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Adds extern "C" { } blocks to header files so that they can be
safely used by C++ source files.
Change-Id: Ia4db0c36a5dac5d3de351184a297d2af0df64532
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
We can save a great deal of RAM this way, it only needs to be
in RAM if dynamic interrupts are in use.
At some point this config option broke, probably when static
interrupts were introduced into the system.
To induce build (instead of runtime) errors when irq_connect_dynamic()
is used without putting the table in RAM, the dynamic interrupt
functions are now conditionally compiled.
Change-Id: I4860508746fd375d189390163876c59b6c544c9a
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This is needed for setting up an image that runs entirely from SRAM,
including its vector table. Ensure integrity of relocated vector table
by using serialization instructions when moving the vector table to
ensure it has been fully written before something makes use of it.
Change-Id: I00c600d557c87c75847f67fbc42f1c2c16157608
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
The interrupt API has been redesigned:
- irq_connect() for dynamic interrupts renamed to irq_connect_dynamic().
It will be used in situations where the new static irq_connect()
won't work, i.e. the value of arguments can't be computed at build time
- a new API for static interrupts replaces irq_connect(). it is used
exactly the same way as its dynamic counterpart. The old static irq
macros will be removed
- Separate stub assembly files are no longer needed as the stubs are now
generated inline with irq_connect()
ReST documentation updated for the changed API. Some detail about the
IDT in ROM added, and an oblique reference to the internal-only
_irq_handler_set() API removed; we don't talk about internal APIs in
the official documentation.
Change-Id: I280519993da0e0fe671eb537a876f67de33d3cd4
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Change terminology and use SoC instead of platform. An SoC provides
features and default configurations available with an SoC. A board
implements the SoC and adds more features and IP block specific to the
board to extend the SoC functionality such as sensors and debugging
features.
Change-Id: I15e8d78a6d4ecd5cfb3bc25ced9ba77e5ea1122f
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Removed old style file description and documnetation and apply
doxygen synatx.
Change-Id: I3ac9f06d4f574bf3c79c6f6044cec3a7e2f6e4c8
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Removes the 'priority' parameter from the IRQ_CONFIG macro.
This parameter was not used anymore in any architecture.
The priority is handled in the IRQ_CONNECT macro.
The documentation is updated as well.
Change-Id: I24a293c5e41bd729d5e759113e0c4a8a6a61e0dd
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
This way, it does not fall in the middle of a group, like the RAM group
and as a side-effect potentially move the dot (current address pointer).
Change-Id: Iefbff8bbeadfc740dee61154d7db99b7b7aad6d6
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Initialization level can be one of five predefined.
Init priority is numeric from 1 to 99. If init level or priority
is defined wrong, linker prints out the message and stops.
Change-Id: I165a32ffb668cda983fd48eb2aa7b94998e31a18
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
Flags allow passing IRQ triggering option for x86 architecture.
Each platform defines flags for a particular device and then
device driver uses them when registers the interrupt handler.
The change in API means that device drivers and sample
applications need to use the new API.
IRQ triggering configuration is now handled by device drivers
by using flags passed to interrupt registering API:
IRQ_CONNECT_STATIC() or irq_connect()
Change-Id: Ibc4312ea2b4032a2efc5b913c6389f780a2a11d1
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
Remove prototype support for C++ constructors, since it is not well
designed. Device drivers (or other application code) that requires an
automatic initialization capability should use the device initialization
macros instead.
Note: Support for C++ constructors may be re-introduced at a later date.
However, a number of issues need to be settled, such as when the
constructors are invoked and what context they run in. (Running them
during nanokernel initialization, as was previously done, is probably
not the right approach.)
Change-Id: If6d27ac16b485cb39d5ec34084e9d0f1991074f4
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
These symbols have more meaningful names when trying to figure out where
the ROM/RAM starts/ends, rather than relying on e.g. __data_rom_start for
the end of the ROM (__data_rom_start is the beginning of the data in
ROM, thus is not part of the image).
Change-Id: I4aa0354ee414fd0d46d0f40952e091ba090e7bce
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
ARM targets now have access to the address types 'paddr_t' and 'vaddr_t'.
Change-Id: Ic7225647f3776d4afa853cf2c4a19699b656866a
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
This patch enables defining microkernel events within source code.
This is similar to other private kernel object patches.
The test has been modified a little bit due to the fact that
the event ID is now a memory address, instead of numeric ID.
Change-Id: Ie3c8d4f4e459d9c631e50bb242cf7a05ca8ea82c
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Change-Id: I819d13f0d7a23e3a61dcda6a3ced18810b192158
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Change-Id: I6da43e41f9c6efee577b70513ec368ae3cce0144
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
In order to have drivers that are usable cross architecture the
signature for IRQ_CONFIG needs to be the same to avoid #ifdef hell in
the driver code based on architecture.
Update the macro and it usage for existing drivers
Change-Id: I22e142b21d4e984add231d1dbd97020e4823985f
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Introduces the SYS_DEFINE_DEVICE() macro, which supports 5 distinct
levels of device initialization and 100 priorities within each level.
Note: The existing init macros (e.g. nano_early_init()) have been
adapted to utilize the enhanced initialization model, but will
eventually be retired.
Change-Id: If677029d8b711a3fae9b2f32b5470cd97d19aeda
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
Change all the Intel and Wind River code license from BSD-3 to Apache 2.
Change-Id: Id8be2c1c161a06ea8a0b9f38e17660e11dbb384b
Signed-off-by: Javier B Perez Hernandez <javier.b.perez.hernandez@linux.intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Due to similar padding issue as pipe, the list of task object
may not be used directly. As mentioned before, some compiler/linker
may pad the large struct. For example, compiling under gcc and
march=i686 pads the struct to 32-byte alignment (march=atom to
64-byte alignment). This causes issue with sizeof() and pointer
arithmetic because they have no idea about the padding.
When the stars align in a certain way, these task structs may be
corrupted. So add a task pointer list and use it for task
manipulation. The task list remains as it is beneficial to group
them together to take advantage of cache locality.
Change-Id: I0e86bfe05742040f4540d7854c1ac14e76162776
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The term 'context' is vague and overloaded. Its usage for 'an execution
context' is now referred as such, in both comments and some APIs' names.
When the execution context can only be a fiber or a task (i.e. not an
ISR), it is referred to as a 'thread', again in comments and everywhere
in the code.
APIs that had their names changed:
- nano_context_id_t is now nano_thread_id_t
- context_self_get() is now sys_thread_self_get()
- context_type_get() is now sys_execution_context_type_get()
- context_custom_data_set/get() are now
sys_thread_custom_data_set/get()
The 'context' prefix namespace does not have to be reserved by the
kernel anymore.
The Context Control Structure (CCS) data structure is now the Thread
Control Structure (TCS):
- struct ccs is now struct tcs
- tCCS is now tTCS
Change-Id: I7526a76c5b01e7c86333078e2d2e77c9feef5364
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Highlight the fact that find_[lsb|msb]_set operate on a 32-bit word.
Change-Id: I24cee7709ea6497508dbc7f96a7b4d74fa4bc257
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
The new names reflect better what the functions do: they find the first
bit set starting from the least or most significant bit, i.e. they find
the least or most significant bit set, in a 32-bit word.
Change-Id: I6f0ee4b543f6f37c2f08f7067e14e039c92a6f6a
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
The inline versions are renamed to remove the _inline suffix, and the
non-inline versions are removed from the code base.
Change-Id: Iee2e6adcfb5da1fe0a978a05aa854e10ae82a8b8
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
The inline versions are renamed to remove the _inline suffix, and the
non-inline versions are removed from the code base.
Change-Id: I7314b96c42835f15df4c537ec11ab7961d4ee60f
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
irq_handler_set, irq_priority_set and irq_disconnect have been made
private by prepending an underscore to their names:
irq_handler_set -> irq_handler_set
irq_priority_set -> irq_priority_set
irq_disconnect -> irq_disconnect
The prototypes have been removed from header files when possible, and
extern statements used in C code where they were called.
_irq_priority_set() for ARM is still in the header file because
IRQ_CONFIG() relies on it.
Change-Id: I2ad585f8156ff80250f6d9eeca4a249a4477fd9d
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
This enable defining memory maps in source code in addition to
defining in MDEF files. This introduces the macro
DEFINE_MEM_MAP(mem_map_name, ...). The memory maps created this
way are the same, in functionality, as those defined in MDEF
files. They can be manipulated by the standard microkernel
memory map APIs.
Define the memory map using:
DEFINE_MEM_MAP(mem_map1, blocks, block_size);
and "mem_map1" can be used, for example:
task_mem_map_alloc(mem_map1, ...);
or,
task_mem_map_free(mem_map1, ...);
etc.
To use the memory map defined in another source file, simply add:
extern const kmemory_map_t mem_map1;
to the desired C or header file.
Change-Id: I9c551b90f9d0a95f961fd8ec1c5278c2ea44312d
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The _k_mem_map_list was a static array generated by sysgen,
where it containing all pre-defined memory maps from MDEF file.
To support private memory map objects (aka, defining them within
source files), the list has to accommodate memory maps that
are not only processed through sysgen, but also those defined
within source files.
This is done by creating a new section in binary, and all memory
map pointers go into this section. By doing this, the list
can still be manipulated as an array.
Change-Id: I1f3414b72f685fef4b99850749178661f14d9345
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This enable defining pipes in source code in addition to
defining in MDEF files. This introduces the macro
DEFINE_PIPE(pipe_name, ...). The pipes created this
way are the same, in functionality, as those defined in MDEF
files. They can be manipulated by the standard microkernel
pipe APIs.
Define the pipe using:
DEFINE_PIPE(pipe1, size);
and "pipe1" can be used, for example:
task_pipe_put(pipe1, ...);
or,
task_pipe_get(pipe1, ...);
etc.
To use the pipe defined in another source file, simply add:
extern const kpipe_t pipe1;
to the desired C or header file.
Change-Id: Iae8e04706359bc18aae51acc75df3e3d26388882
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
