Adds a new test for the SPI_DT_SPEC initializer macro to reproduce the
XCC build failure reported in #43745 on the intel_adsp_cavs15 board.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
The SAM spi driver depends on GPIO driver to work. It seems that this
dependency chain it is not handled. This select GPIO driver when SPI
driver is enabled. It rework GPIO and SPI Kconfig to select driver by
devicetree and drop entries at Kconfig.defconfig.series file.
Fixes#41525
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
The testcase is including a generic configuration conf
for the stm32 target boards when running the SPI loopback in
interrupt and DMA mode. Thus, the board specific conf file is useless.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit adds two stm32 config to execute the testcase
when the SPI is using interrupt mode for transfer.
when the SPI is using DMA for transfer (not Interrupt nor ASYNC mode).
to run the on some specific (listed) stm32 boards on SPI instance.
Note the hw fixture (physical connection on the board)
Signed-off-by: Francois Ramu <francois.ramu@st.com>
with this config, the testcase PASSED on the nucleo_h743zi
using DMA for SPI transfer (through DMAMUX request)
Connect pins D11 and D12 on the ARDUIno connector CN7
Signed-off-by: Francois Ramu <francois.ramu@st.com>
connect SPI1 MISO pin D12 (pa6) on SPI1 MOSI pin D11 (pa7)
on the ARDuino connector CN5 of the nucleo board
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add support for LPSPI DMA mode on RT1064, RT1060, RT1050, RT1024,
RT1020, RT1015, and RT1010 evaluation boards. Update tests to match.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add support of the tests/drivers/spi/spi_loopabck
with dma (V1).
Connect MISO pin (D12) to MOSI (D11) pin on the board
to pass the test.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This patch is defining Tx buffers in NON CACHE memory for using
with DMA transfers. This requires the CONFIG_NOCACHE_MEMORY=y
flag when mcu is using CACHE.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Adds SPI support on LPSPI1 to the RT1010. LPSPI1 is available on pins
6, 8, 10, and 12 of J57 on the evaluation board
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This commit enables the LPSPI1 peripheral on the RT1015 EVK. LPSPI pins
are not populated by default, but headers can be added to J19 on the EVK
to access these signals
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add support for LPSPI to mimxrt1024_evk. LPSPI1 is exposed on pins
6,8,10, and 12 of J19 of the evaluation board
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
SPI support is available on LPSPI1 and LPSPI3. Both of these require
board modifications to expose headers. LPSPI1 is used for testing,
and requires that the board have solder jumpers R278, R279, R280,
and R281 bridged.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
SPI support is available on LPSPI1 and LPSPI3. Both of these require
board modifications to expose headers. LPSPI1 is used for testing, and
requires that the board have solder jumpers R278, R279, R280, and R281
bridged.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
RT1050 has multiple LPSPI peripherals. The simplest to access is LPSPI1,
which can be connected by bridging solder jumpers on the board. Enable
this SPI peripheral, and set it as default for SPI tests.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Configure the target board to PASS the test case.
The PCLK2 clock feeding the SPI1 is reduced by 2 (apb2 prescaler)
to accept the slow freq config.
The SPI1 MISO and MOSI pins are linked on the HW board
(on arduino CN13, D11 & D12)
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Move to CMake 3.20.0.
At the Toolchain WG it was decided to move to CMake 3.20.0.
The main reason for increasing CMake version is better toolchain
support.
Better toolchain support is added in the following CMake versions:
- armclang, CMake 3.15
- Intel oneAPI, CMake 3.20
- IAR, CMake 3.15 and 3.20
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
add configuration for testing the spi through the dma1
on the nucleo_l152re target. This test requires the MOSI pin
to be connected to the MISO pin on the board.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Based on the new bindings for the stm32 dma feature,
the overlay for enabling the dmamux on spi client is modified.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit configures spi, dma & dmamux to run spi_loopback test
on nucleo_l552ze_q platform. The tx & rx pin of spi1 should be
shorted before running spi_loopback.
Signed-off-by: Krishna Mohan Dani <krishnamohan.d@hcl.com>
Rename the NXP LPCXpresso55S16 board definition from
lpcxpresso55s16_ns (non-secure) to lpcxpresso55s16 and remove TF-M
configuration options.
While the LPC55S16 does have Arm TrustZone support, there is no TF-M
support available upstream yet.
Fixes#35100
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
As the nucleo_g474re was converted to define clock properties
in devicetree, this commit makes the ncecessary changes such that
the ncecessary test properties are still applied.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Add nucleo_g431rb to spi_loopback test using spi async configuration.
Such that tests do not only run with syncronous spi configuration
(nucleo_g474re), but also with the asyncronous configuration.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
This commit enables test_spi_loopback sample application for
Nucleo_F207zg. test_spi_loopback was executed under the following case
sceanarios on SPI-1:
a. With DMA
b. No DMA - No Interrrupts
c. No DMA - Interrupts Enabled
Signed-off-by: Krishna Mohan Dani <krishnamohan.d@hcl.com>
The spi loopback tests enables SPI ASYNC which for the SAM0 SPI driver
requires DMA support is configured. None of the current SAM0 based
boards configure DMA for SPI and thus we exclude these boards as the
test will not compile for these boards.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Enable by default the use of RAM buffers in the spi_nrfx_spim.c
driver for copying TX data located in flash (as SPIM peripherals
cannot transfer directly form flash). Without this patch, users can
get confused, especially when SPI transaction is used by an upper
level driver which does not check all error codes.
For size of the buffer, use the value used so far in the reel_board
default configuration and in the SPI loopback test, i.e. 8 bytes.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Now that device_api attribute is unmodified at runtime, as well as all
the other attributes, it is possible to switch all device driver
instance to be constant.
A coccinelle rule is used for this:
@r_const_dev_1
disable optional_qualifier
@
@@
-struct device *
+const struct device *
@r_const_dev_2
disable optional_qualifier
@
@@
-struct device * const
+const struct device *
Fixes#27399
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Add support for running the SPI loopback driver test on the ARM
Cortex-M1 DesignStart FPGA reference design.
Since Xilinx AXI Quad SPI IP only supports loopback mode when configured
for single line SPI width, we utilise the (normally disabled) single SPI
instance going to the optional V2C DAPLINK shield SD card slot for
testing purposes.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
