Bluetooth: Controller: CCM read data to early when DF enabled on PHY 1M
CCM during on-the-fly decryption of a received packet starts decryption when Radio triggers EVETNS_ADDRESS. In case there is possibility a packet may include Constant Tone Extension, on-the-fly parsing of a received packet for CTEInfo is enabled. If there is a PHY 1M enabled the Radio stores received bits with a delay, that is equal to time required to receive 3 bits. CCM TASKS_CRYPT related with packet decryption should be delayed by the time the Radio needs to store received data. The commit provides changes required to delay start of the CCM TASKS_CRYPT. It uses NRF_RADIO Bit counter feature. The Bit counter is configured to trigger NRF_RADIO->EVENTS_BCMATCH on reception of 3rd bit. The event is connected through PPI with CCM TASKS_CRYPT. The PPI used is shared with Radio Rate override. That is possible because direction finding feature is not allowed on PHY Coded and CCM needs a delay only when used PHY 1M. Signed-off-by: Piotr Pryga <piotr.pryga@nordicsemi.no>
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@ -103,6 +103,13 @@
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#define HAL_USED_PPI_CHANNELS_7 0
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#endif /* CONFIG_BT_CTLR_DF_PHYEND_OFFSET_COMPENSATION_ENABLE */
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#if defined(CONFIG_BT_CTLR_DF_CONN_CTE_RX)
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#define HAL_USED_PPI_CHANNELS_8 \
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BIT(HAL_TRIGGER_CRYPT_DELAY_PPI)
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#else
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#define HAL_USED_PPI_CHANNELS_8 0
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#endif /* CONFIG_BT_CTLR_DF_CONN_CTE_RX */
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/* Mask with all (D)PPI groups used by the bluetooth controller. */
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#if defined(SW_SWITCH_TIMER_TASK_GROUP_BASE)
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#define BT_CTLR_USED_PPI_GROUPS \
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@ -512,6 +512,7 @@ void radio_status_reset(void)
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/* Clear it only for SoCs supporting DF extension */
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NRF_RADIO->EVENTS_PHYEND = 0;
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NRF_RADIO->EVENTS_CTEPRESENT = 0;
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NRF_RADIO->EVENTS_BCMATCH = 0;
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#endif /* CONFIG_BT_CTLR_DF_SUPPORT && !CONFIG_ZTEST */
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NRF_RADIO->EVENTS_DISABLED = 0;
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#if defined(CONFIG_BT_CTLR_PHY_CODED)
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@ -1031,6 +1032,9 @@ void radio_tmr_status_reset(void)
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#if defined(CONFIG_BT_CTLR_DF_PHYEND_OFFSET_COMPENSATION_ENABLE)
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BIT(HAL_SW_SWITCH_TIMER_PHYEND_DELAY_COMPENSATION_DISABLE_PPI) |
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#endif /* CONFIG_BT_CTLR_DF_PHYEND_OFFSET_COMPENSATION_ENABLE */
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#if defined(CONFIG_BT_CTLR_DF_CONN_CTE_RX)
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BIT(HAL_TRIGGER_CRYPT_DELAY_PPI) |
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#endif /* CONFIG_BT_CTLR_DF_CONN_CTE_RX */
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BIT(HAL_TRIGGER_CRYPT_PPI));
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}
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@ -1494,12 +1498,30 @@ void *radio_ccm_rx_pkt_set(struct ccm *ccm, uint8_t phy, void *pkt)
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mode |= (CCM_MODE_DATARATE_1Mbit <<
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CCM_MODE_DATARATE_Pos) &
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CCM_MODE_DATARATE_Msk;
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#if defined(CONFIG_BT_CTLR_DF_CONN_CTE_RX)
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/* When direction finding CTE receive feature is enabled then on-the-fly PDU
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* parsing for CTEInfo is always done. In such situation, the CCM TASKS_CRYPT
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* must be started with short delay. That give the Radio time to store received bits
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* in shared memory.
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*/
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radio_bc_configure(CCM_TASKS_CRYPT_DELAY_BITS);
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radio_bc_status_reset();
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hal_trigger_crypt_by_bcmatch_ppi_config();
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hal_radio_nrf_ppi_channels_enable(BIT(HAL_TRIGGER_CRYPT_DELAY_PPI));
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#else
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hal_trigger_crypt_ppi_config();
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hal_radio_nrf_ppi_channels_enable(BIT(HAL_TRIGGER_CRYPT_PPI));
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#endif /* CONFIG_BT_CTLR_DF_CONN_CTE_RX */
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break;
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case PHY_2M:
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mode |= (CCM_MODE_DATARATE_2Mbit <<
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CCM_MODE_DATARATE_Pos) &
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CCM_MODE_DATARATE_Msk;
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hal_trigger_crypt_ppi_config();
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hal_radio_nrf_ppi_channels_enable(BIT(HAL_TRIGGER_CRYPT_PPI));
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break;
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#if defined(CONFIG_BT_CTLR_PHY_CODED)
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@ -1517,6 +1539,10 @@ void *radio_ccm_rx_pkt_set(struct ccm *ccm, uint8_t phy, void *pkt)
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hal_trigger_rateoverride_ppi_config();
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hal_radio_nrf_ppi_channels_enable(
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BIT(HAL_TRIGGER_RATEOVERRIDE_PPI));
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hal_trigger_crypt_ppi_config();
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hal_radio_nrf_ppi_channels_enable(BIT(HAL_TRIGGER_CRYPT_PPI));
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break;
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#endif /* CONFIG_HAS_HW_NRF_RADIO_BLE_CODED */
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#endif /* CONFIG_BT_CTLR_PHY_CODED */
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@ -1538,12 +1564,10 @@ void *radio_ccm_rx_pkt_set(struct ccm *ccm, uint8_t phy, void *pkt)
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NRF_CCM->OUTPTR = (uint32_t)pkt;
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NRF_CCM->SCRATCHPTR = (uint32_t)_ccm_scratch;
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NRF_CCM->SHORTS = 0;
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NRF_CCM->EVENTS_ENDKSGEN = 0;
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NRF_CCM->EVENTS_ENDCRYPT = 0;
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NRF_CCM->EVENTS_ERROR = 0;
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hal_trigger_crypt_ppi_config();
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hal_radio_nrf_ppi_channels_enable(BIT(HAL_TRIGGER_CRYPT_PPI));
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nrf_ccm_task_trigger(NRF_CCM, NRF_CCM_TASK_KSGEN);
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return _pkt_scratch;
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@ -1574,6 +1598,7 @@ void *radio_ccm_tx_pkt_set(struct ccm *ccm, void *pkt)
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NRF_CCM->OUTPTR = (uint32_t)_pkt_scratch;
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NRF_CCM->SCRATCHPTR = (uint32_t)_ccm_scratch;
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NRF_CCM->SHORTS = CCM_SHORTS_ENDKSGEN_CRYPT_Msk;
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NRF_CCM->EVENTS_ENDKSGEN = 0;
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NRF_CCM->EVENTS_ENDCRYPT = 0;
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NRF_CCM->EVENTS_ERROR = 0;
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@ -29,6 +29,9 @@
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#define RADIO_EVENTS_PHYEND_DELAY_US 16
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#endif /* CONFIG_BT_CTLR_DF_PHYEND_OFFSET_COMPENSATION_ENABLE */
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/* Delay of CCM TASKS_CRYPT start in number of bits for Radio Bit counter */
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#define CCM_TASKS_CRYPT_DELAY_BITS 3
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/* EVENTS_TIMER capture register used for sampling TIMER time-stamps. */
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#define HAL_EVENT_TIMER_SAMPLE_CC_OFFSET 3
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#define HAL_EVENT_TIMER_SAMPLE_TASK NRF_TIMER_TASK_CAPTURE3
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@ -130,6 +130,32 @@ static inline void hal_trigger_crypt_ppi_config(void)
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nrf_ccm_subscribe_set(NRF_CCM, NRF_CCM_TASK_CRYPT, HAL_RADIO_RECV_TIMEOUT_CANCEL_PPI);
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}
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#if defined(CONFIG_BT_CTLR_DF_CONN_CTE_RX)
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/*******************************************************************************
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* Trigger encryption task on Bit counter match:
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* wire the RADIO EVENTS_BCMATCH event to the CCM TASKS_CRYPT task.
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*
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* PPI channel HAL_TRIGGER_CRYPT_DELAY_PPI is also used for HAL_TRIGGER-
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* _RATEOVERRIDE_PPI.
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* Make sure the same PPI is not configured for both events at once.
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*
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* EEP: RADIO->EVENTS_BCMATCH
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* TEP: CCM->TASKS_CRYPT
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*/
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static inline void hal_trigger_crypt_by_bcmatch_ppi_config(void)
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{
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/* Configure Bit counter to trigger EVENTS_BCMATCH for CCM_TASKS_CRYPT-
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* _DELAY_BITS bit. This is a time required for Radio to store
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* received data in memory before the CCM TASKS_CRYPT starts. This
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* makes CCM to do not read the memory before Radio stores received
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* data.
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*/
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nrf_radio_publish_set(NRF_RADIO,
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NRF_RADIO_EVENT_BCMATCH, HAL_TRIGGER_CRYPT_DELAY_PPI);
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nrf_ccm_subscribe_set(NRF_CCM, NRF_CCM_TASK_CRYPT, HAL_TRIGGER_CRYPT_DELAY_PPI);
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}
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#endif /* CONFIG_BT_CTLR_DF_CONN_CTE_RX */
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/*******************************************************************************
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* Trigger automatic address resolution on Bit counter match:
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* wire the RADIO EVENTS_BCMATCH event to the AAR TASKS_START task.
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@ -141,6 +141,17 @@
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#define HAL_SW_SWITCH_TIMER_PHYEND_DELAY_COMPENSATION_DISABLE_PPI 16
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#endif /* CONFIG_BT_CTLR_DF_PHYEND_OFFSET_COMPENSATION_ENABLE */
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#if defined(CONFIG_BT_CTLR_DF_CONN_CTE_RX)
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/* Trigger encryption task upon bit counter match event fire:
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* wire the RADIO EVENTS_BCMATCH event to the CCM TASKS_CRYPT task.
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*
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* Note: The PPI number is shared with HAL_TRIGGER_RATEOVERRIDE_PPI because it is used only
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* when direction finding RX and PHY is set to PHY1M. Due to that it can be shared with Radio Rate
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* override.
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*/
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#define HAL_TRIGGER_CRYPT_DELAY_PPI 13
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#endif /* CONFIG_BT_CTLR_DF_CONN_CTE_RX */
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/* The 2 adjacent PPI groups used for implementing SW_SWITCH_TIMER-based
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* auto-switch for TIFS. 'index' must be 0 or 1.
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*/
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@ -184,6 +184,32 @@ static inline void hal_trigger_crypt_ppi_config(void)
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/* No need to configure anything for the pre-programmed channel. */
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}
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#if defined(CONFIG_BT_CTLR_DF_CONN_CTE_RX)
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/*******************************************************************************
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* Trigger encryption task on Bit counter match:
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* wire the RADIO EVENTS_BCMATCH event to the CCM TASKS_CRYPT task.
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*
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* PPI channel HAL_TRIGGER_CRYPT_DELAY_PPI is also used for HAL_TRIGGER-
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* _RATEOVERRIDE_PPI.
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* Make sure the same PPI is not configured for both events at once.
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*
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* EEP: RADIO->EVENTS_BCMATCH
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* TEP: CCM->TASKS_CRYPT
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*/
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static inline void hal_trigger_crypt_by_bcmatch_ppi_config(void)
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{
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/* Configure Bit counter to trigger EVENTS_BCMATCH for CCM_TASKS_CRYPT-
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* _DELAY_BITS bit. This is a time required for Radio to store
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* received data in memory before the CCM TASKS_CRYPT starts. This
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* makes CCM to do not read the memory before Radio stores received
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* data.
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*/
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nrf_ppi_channel_endpoint_setup(NRF_PPI, HAL_TRIGGER_CRYPT_DELAY_PPI,
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(uint32_t)&(NRF_RADIO->EVENTS_BCMATCH),
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(uint32_t)&(NRF_CCM->TASKS_CRYPT));
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}
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#endif /* CONFIG_BT_CTLR_DF_CONN_CTE_RX */
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/*******************************************************************************
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* Trigger automatic address resolution on Bit counter match:
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* wire the RADIO EVENTS_BCMATCH event to the AAR TASKS_START task.
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@ -179,6 +179,17 @@
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#define HAL_SW_SWITCH_TIMER_PHYEND_DELAY_COMPENSATION_DISABLE_PPI 19
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#endif /* CONFIG_BT_CTLR_DF_PHYEND_OFFSET_COMPENSATION_ENABLE */
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#if defined(CONFIG_BT_CTLR_DF_CONN_CTE_RX)
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/* Trigger encryption task upon bit counter match event fire:
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* wire the RADIO EVENTS_BCMATCH event to the CCM TASKS_CRYPT task.
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*
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* Note: The PPI number is shared with HAL_TRIGGER_RATEOVERRIDE_PPI because it is used only
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* when direction finding RX and PHY is set to PHY1M. Due to that it can be shared with Radio Rate
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* override.
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*/
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#define HAL_TRIGGER_CRYPT_DELAY_PPI 14
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#endif /* CONFIG_BT_CTLR_DF_CONN_CTE_RX */
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/* The 2 adjacent PPI groups used for implementing SW_SWITCH_TIMER-based
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* auto-switch for TIFS. 'index' must be 0 or 1.
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*/
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