diff --git a/boards/x86/ehl_crb/Kconfig.defconfig b/boards/x86/ehl_crb/Kconfig.defconfig index c7ed624ef5b..b32c4bf727b 100644 --- a/boards/x86/ehl_crb/Kconfig.defconfig +++ b/boards/x86/ehl_crb/Kconfig.defconfig @@ -1,9 +1,10 @@ # Copyright (c) 2020 Intel Corporation # SPDX-License-Identifier: Apache-2.0 -if BOARD_EHL_CRB +if BOARD_EHL_CRB || BOARD_EHL_CRB_SBL config BOARD + default "ehl_crb_sbl" if BOARD_EHL_CRB_SBL default "ehl_crb" config BUILD_OUTPUT_STRIPPED @@ -12,21 +13,28 @@ config BUILD_OUTPUT_STRIPPED config MP_NUM_CPUS default 2 -endif # BOARD_EHL_CRB - if BOARD_EHL_CRB_SBL - -config BOARD - default "ehl_crb_sbl" - -config BUILD_OUTPUT_STRIPPED - default y - -config MP_NUM_CPUS - default 2 - config SHELL_BACKEND_SERIAL_INTERRUPT_DRIVEN depends on SHELL_BACKEND_SERIAL default n +endif -endif # BOARD_EHL_CRB_SBL +config HPET_TIMER + default y + +# TSC on this board is 1.9 GHz, HPET and APIC are 19.2 MHz +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 1900000000 if APIC_TSC_DEADLINE_TIMER + default 1900000000 if APIC_TIMER_TSC + default 19200000 + +if APIC_TIMER +config APIC_TIMER_IRQ + default 24 +config APIC_TIMER_TSC_M + default 3 +config APIC_TIMER_TSC_N + default 249 +endif + +endif # BOARD_EHL_CRB || BOARD_EHL_CRB_SBL diff --git a/soc/x86/elkhart_lake/Kconfig.defconfig b/soc/x86/elkhart_lake/Kconfig.defconfig index fe4a08093de..99332ddce2f 100644 --- a/soc/x86/elkhart_lake/Kconfig.defconfig +++ b/soc/x86/elkhart_lake/Kconfig.defconfig @@ -9,38 +9,9 @@ if SOC_ELKHART_LAKE config SOC default "elkhart_lake" -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 19200000 - -config HPET_TIMER - default y - -config APIC_TIMER - default y if !HPET_TIMER - config PCIE_MMIO_CFG default y -if APIC_TIMER - -config APIC_TIMER_IRQ - default 24 - -config APIC_TIMER_TSC - default y - -if APIC_TIMER_TSC - -config APIC_TIMER_TSC_M - default 3 - -config APIC_TIMER_TSC_N - default 249 - -endif # APIC_TIMER_TSC - -endif # APIC_TIMER - config X86_DYNAMIC_IRQ_STUBS default 16 depends on DYNAMIC_INTERRUPTS