diff --git a/drivers/clock_control/clock_stm32_ll_common.c b/drivers/clock_control/clock_stm32_ll_common.c
index 87a69e9214d..c74477e2373 100644
--- a/drivers/clock_control/clock_stm32_ll_common.c
+++ b/drivers/clock_control/clock_stm32_ll_common.c
@@ -483,7 +483,7 @@ static int stm32_clock_control_get_subsys_rate(const struct device *clock,
 #endif /* STM32_HSI48_ENABLED */
 #if defined(STM32_CK48_ENABLED)
 	case STM32_SRC_CK48:
-		*rate = STM32_CK48_FREQ;
+		*rate = get_ck48_frequency();
 		break;
 #endif /* STM32_CK48_ENABLED */
 
diff --git a/drivers/clock_control/clock_stm32_ll_common.h b/drivers/clock_control/clock_stm32_ll_common.h
index 8c63778ca11..1988bb06544 100644
--- a/drivers/clock_control/clock_stm32_ll_common.h
+++ b/drivers/clock_control/clock_stm32_ll_common.h
@@ -61,6 +61,10 @@ void config_enable_default_clocks(void);
 void config_regulator_voltage(uint32_t hclk_freq);
 int enabled_clock(uint32_t src_clk);
 
+#if defined(STM32_CK48_ENABLED)
+uint32_t get_ck48_frequency(void);
+#endif
+
 /* functions exported to the soc power.c */
 int stm32_clock_control_init(const struct device *dev);
 void stm32_clock_control_standby_exit(void);
diff --git a/drivers/clock_control/clock_stm32f2_f4_f7.c b/drivers/clock_control/clock_stm32f2_f4_f7.c
index cf69948d949..59f78867542 100644
--- a/drivers/clock_control/clock_stm32f2_f4_f7.c
+++ b/drivers/clock_control/clock_stm32f2_f4_f7.c
@@ -50,6 +50,46 @@ uint32_t get_pllsrc_frequency(void)
 	return 0;
 }
 
+#if defined(STM32_CK48_ENABLED)
+/**
+ * @brief calculate the CK48 frequency depending on its clock source
+ */
+__unused
+uint32_t get_ck48_frequency(void)
+{
+	uint32_t source;
+
+	if (LL_RCC_GetCK48MClockSource(LL_RCC_CK48M_CLKSOURCE) ==
+			LL_RCC_CK48M_CLKSOURCE_PLL) {
+		/* Get the PLL48CK source : HSE or HSI */
+		source = (LL_RCC_PLL_GetMainSource() == LL_RCC_PLLSOURCE_HSE)
+			? HSE_VALUE
+			: HSI_VALUE;
+		/* Get the PLL48CK Q freq. No HAL macro for that */
+		return __LL_RCC_CALC_PLLCLK_48M_FREQ(source,
+						LL_RCC_PLL_GetDivider(),
+						LL_RCC_PLL_GetN(),
+						LL_RCC_PLL_GetQ()
+						);
+	} else if (LL_RCC_GetCK48MClockSource(LL_RCC_CK48M_CLKSOURCE) ==
+			LL_RCC_CK48M_CLKSOURCE_PLLI2S) {
+		/* Get the PLL I2S source : HSE or HSI */
+		source = (LL_RCC_PLLI2S_GetMainSource() == LL_RCC_PLLSOURCE_HSE)
+			? HSE_VALUE
+			: HSI_VALUE;
+		/* Get the PLL I2S Q freq. No HAL macro for that */
+		return __LL_RCC_CALC_PLLI2S_48M_FREQ(source,
+						LL_RCC_PLLI2S_GetDivider(),
+						LL_RCC_PLLI2S_GetN(),
+						LL_RCC_PLLI2S_GetQ()
+						);
+	}
+
+	__ASSERT(0, "Invalid source");
+	return 0;
+}
+#endif
+
 /**
  * @brief Set up pll configuration
  */