diff --git a/soc/nordic/common/soc_secure.h b/soc/nordic/common/soc_secure.h
index cb7054962f2..e4b34a9bf64 100644
--- a/soc/nordic/common/soc_secure.h
+++ b/soc/nordic/common/soc_secure.h
@@ -34,7 +34,8 @@ static inline int soc_secure_mem_read(void *dst, void *src, size_t len)
 /* Include these soc_secure_* functions only when the FICR is mapped as secure only */
 #if defined(NRF_FICR_S)
 #if defined(CONFIG_TRUSTED_EXECUTION_NONSECURE)
-#if defined(CONFIG_SOC_HFXO_CAP_INTERNAL)
+#if defined(CONFIG_SOC_HFXO_CAP_INTERNAL) || \
+	DT_ENUM_HAS_VALUE(DT_NODELABEL(hfxo), load_capacitors, internal)
 static inline uint32_t soc_secure_read_xosc32mtrim(void)
 {
 	uint32_t xosc32mtrim;
@@ -60,7 +61,8 @@ static inline void soc_secure_read_deviceid(uint32_t deviceid[2])
 }
 
 #else /* defined(CONFIG_TRUSTED_EXECUTION_NONSECURE) */
-#if defined(CONFIG_SOC_HFXO_CAP_INTERNAL)
+#if defined(CONFIG_SOC_HFXO_CAP_INTERNAL) || \
+	DT_ENUM_HAS_VALUE(DT_NODELABEL(hfxo), load_capacitors, internal)
 static inline uint32_t soc_secure_read_xosc32mtrim(void)
 {
 	return NRF_FICR_S->XOSC32MTRIM;
diff --git a/soc/nordic/nrf53/soc.c b/soc/nordic/nrf53/soc.c
index 46e8e5ca20d..35a13be1b9a 100644
--- a/soc/nordic/nrf53/soc.c
+++ b/soc/nordic/nrf53/soc.c
@@ -56,6 +56,37 @@
 	DT_FOREACH_CHILD(node_id, ALL_GPIOS_IN_NODE)
 #endif
 
+#ifdef CONFIG_SOC_NRF5340_CPUAPP
+#define LFXO_NODE DT_NODELABEL(lfxo)
+#define HFXO_NODE DT_NODELABEL(hfxo)
+
+/* LFXO config from DT */
+#if DT_ENUM_HAS_VALUE(LFXO_NODE, load_capacitors, external)
+#define LFXO_CAP NRF_OSCILLATORS_LFXO_CAP_EXTERNAL
+#elif DT_ENUM_HAS_VALUE(LFXO_NODE, load_capacitors, internal)
+#define LFXO_CAP (DT_ENUM_IDX(LFXO_NODE, load_capacitance_picofarad) + 1U)
+#else
+/* LFXO config from legacy Kconfig */
+#if defined(CONFIG_SOC_LFXO_CAP_INT_6PF)
+#define LFXO_CAP NRF_OSCILLATORS_LFXO_CAP_6PF
+#elif defined(CONFIG_SOC_LFXO_CAP_INT_7PF)
+#define LFXO_CAP NRF_OSCILLATORS_LFXO_CAP_7PF
+#elif defined(CONFIG_SOC_LFXO_CAP_INT_9PF)
+#define LFXO_CAP NRF_OSCILLATORS_LFXO_CAP_9PF
+#else
+#define LFXO_CAP NRF_OSCILLATORS_LFXO_CAP_EXTERNAL
+#endif
+#endif
+
+/* HFXO config from DT */
+#if DT_ENUM_HAS_VALUE(HFXO_NODE, load_capacitors, internal)
+#define HFXO_CAP_VAL_X2 (DT_PROP(HFXO_NODE, load_capacitance_femtofarad)) * 2U / 1000U
+#elif defined(CONFIG_SOC_HFXO_CAP_INTERNAL)
+/* HFXO config from legacy Kconfig */
+#define HFXO_CAP_VAL_X2 CONFIG_SOC_HFXO_CAP_INT_VALUE_X2
+#endif
+#endif /* CONFIG_SOC_NRF5340_CPUAPP */
+
 #define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
 LOG_MODULE_REGISTER(soc);
 
@@ -472,15 +503,9 @@ static int nordicsemi_nrf53_init(void)
 	nrf_nvmc_icache_config_set(NRF_NVMC, NRF_NVMC_ICACHE_ENABLE);
 #endif
 
-#if defined(CONFIG_SOC_ENABLE_LFXO)
-	nrf_oscillators_lfxo_cap_set(NRF_OSCILLATORS,
-		IS_ENABLED(CONFIG_SOC_LFXO_CAP_INT_6PF) ?
-			NRF_OSCILLATORS_LFXO_CAP_6PF :
-		IS_ENABLED(CONFIG_SOC_LFXO_CAP_INT_7PF) ?
-			NRF_OSCILLATORS_LFXO_CAP_7PF :
-		IS_ENABLED(CONFIG_SOC_LFXO_CAP_INT_9PF) ?
-			NRF_OSCILLATORS_LFXO_CAP_9PF :
-			NRF_OSCILLATORS_LFXO_CAP_EXTERNAL);
+#ifdef CONFIG_SOC_NRF5340_CPUAPP
+#if defined(LFXO_CAP)
+	nrf_oscillators_lfxo_cap_set(NRF_OSCILLATORS, LFXO_CAP);
 #if !defined(CONFIG_BUILD_WITH_TFM)
 	/* This can only be done from secure code.
 	 * This is handled by the TF-M platform so we skip it when TF-M is
@@ -489,8 +514,8 @@ static int nordicsemi_nrf53_init(void)
 	nrf_gpio_pin_control_select(PIN_XL1, NRF_GPIO_PIN_SEL_PERIPHERAL);
 	nrf_gpio_pin_control_select(PIN_XL2, NRF_GPIO_PIN_SEL_PERIPHERAL);
 #endif /* !defined(CONFIG_BUILD_WITH_TFM) */
-#endif /* defined(CONFIG_SOC_ENABLE_LFXO) */
-#if defined(CONFIG_SOC_HFXO_CAP_INTERNAL)
+#endif /* defined(LFXO_CAP) */
+#if defined(HFXO_CAP_VAL_X2)
 	/* This register is only accessible from secure code. */
 	uint32_t xosc32mtrim = soc_secure_read_xosc32mtrim();
 	/* The SLOPE field is in the two's complement form, hence this special
@@ -515,13 +540,15 @@ static int nordicsemi_nrf53_init(void)
 	 * value between 7.0 pF and 20.0 pF in 0.5 pF steps.
 	 */
 	uint32_t capvalue =
-		((slope + 56) * (CONFIG_SOC_HFXO_CAP_INT_VALUE_X2 - 14)
+		((slope + 56) * (HFXO_CAP_VAL_X2 - 14)
 		 + ((offset - 8) << 4) + 32) >> 6;
 
 	nrf_oscillators_hfxo_cap_set(NRF_OSCILLATORS, true, capvalue);
-#elif defined(CONFIG_SOC_HFXO_CAP_EXTERNAL)
+#elif defined(CONFIG_SOC_HFXO_CAP_EXTERNAL) || \
+	DT_ENUM_HAS_VALUE(HFXO_NODE, load_capacitors, external)
 	nrf_oscillators_hfxo_cap_set(NRF_OSCILLATORS, false, 0);
 #endif
+#endif /* CONFIG_SOC_NRF5340_CPUAPP */
 
 #if defined(CONFIG_SOC_DCDC_NRF53X_APP) || \
 	(DT_PROP(DT_NODELABEL(vregmain), regulator_initial_mode) == NRF5X_REG_MODE_DCDC)