diff --git a/boards/arduino_101/pinmux.c b/boards/arduino_101/pinmux.c
index 4258fd2f453..3a1e3b4772f 100644
--- a/boards/arduino_101/pinmux.c
+++ b/boards/arduino_101/pinmux.c
@@ -193,7 +193,7 @@ static void _pinmux_defaults(uint32_t base)
 	}
 }
 
-static uint32_t _quark_se_pullup(uint32_t base, uint32_t pin, uint8_t func)
+static uint32_t _quark_se_set_mux(uint32_t base, uint32_t pin, uint8_t func)
 {
 	/*
 	 * the registers are 32-bit wide, but each pin requires 1 bit
@@ -203,10 +203,8 @@ static uint32_t _quark_se_pullup(uint32_t base, uint32_t pin, uint8_t func)
 	/*
 	 * Now figure out what is the full address for the register
 	 * we are looking for.  Add the base register to the register_mask
-	 * Valid values include: 0x900, 0x904, 0x908, and 0x90C
 	 */
-	volatile uint32_t *mux_register =
-		(uint32_t *)(base + PINMUX_PULLUP_OFFSET + register_offset);
+	volatile uint32_t *mux_register = (uint32_t *)(base + register_offset);
 
 	/*
 	 * Finally grab the pin offset within the register
@@ -223,38 +221,10 @@ static uint32_t _quark_se_pullup(uint32_t base, uint32_t pin, uint8_t func)
 	return DEV_OK;
 }
 
-static uint32_t _quark_se_input(uint32_t base, uint32_t pin, uint8_t func)
-{
-	/*
-	 * the registers are 32-bit wide, but each pin requires 1 bit
-	 * to set the input enable bit.
-	 */
-	uint32_t register_offset = (pin / 32) * 4;
-	/*
-	 * Now figure out what is the full address for the register
-	 * we are looking for.  Add the base register to the register_mask
-	 * Valid values include: 0x920, 0x924, 0x928, and 0x92C
-	 */
-	volatile uint32_t *mux_register =
-		(uint32_t *)(base + PINMUX_INPUT_OFFSET + register_offset);
-
-	/*
-	 * Finally grab the pin offset within the register
-	 */
-	uint32_t pin_offset = pin % 32;
-
-	/*
-	 * MAGIC NUMBER: 0x1 is used as the pullup is a single bit in a
-	 * 32-bit register.
-	 */
-	(*(mux_register)) = ((*(mux_register)) & ~(0x1 << pin_offset)) |
-		((func & 0x01) << pin_offset);
-
-	return DEV_OK;
-}
 static inline void _pinmux_pullups(uint32_t base_address)
 {
-	_quark_se_pullup(base_address, 104, PINMUX_PULLUP_ENABLE);
+	_quark_se_set_mux(base_address + PINMUX_PULLUP_OFFSET, 104,
+			  PINMUX_PULLUP_ENABLE);
 }
 
 
@@ -356,7 +326,7 @@ static uint32_t pinmux_dev_pullup(struct device *dev,
 {
 	struct pinmux_config * const pmux = dev->config->config_info;
 
-	_quark_se_pullup(pmux->base_address, pin, func);
+	_quark_se_set_mux(pmux->base_address + PINMUX_PULLUP_OFFSET, pin, func);
 
 	return DEV_OK;
 }
@@ -364,7 +334,7 @@ static uint32_t pinmux_dev_input(struct device *dev, uint32_t pin, uint8_t func)
 {
 	struct pinmux_config * const pmux = dev->config->config_info;
 
-	_quark_se_input(pmux->base_address, pin, func);
+	_quark_se_set_mux(pmux->base_address + PINMUX_INPUT_OFFSET, pin, func);
 
 	return DEV_OK;
 }
diff --git a/boards/quark_d2000_crb/pinmux.c b/boards/quark_d2000_crb/pinmux.c
index c81be0defa1..7fb6dff9737 100644
--- a/boards/quark_d2000_crb/pinmux.c
+++ b/boards/quark_d2000_crb/pinmux.c
@@ -40,7 +40,7 @@
 #define MASK_2_BITS			0x3
 const uint32_t PINMUX_PULLUP_OFFSET		= 0x00;
 const uint32_t PINMUX_SLEW_OFFSET		= 0x10;
-const uint32_t PINMUX_INPUT_ENABLE_OFFSET	= 0x20;
+const uint32_t PINMUX_INPUT_OFFSET		= 0x20;
 const uint32_t PINMUX_SELECT_OFFSET		= 0x30;
 
 #define PINMUX_SELECT_REGISTER(base, reg_offset) \
@@ -133,8 +133,7 @@ static void _pinmux_defaults(uint32_t base)
 
 }
 
-
-static void _quark_d2000_pullup_set(uint32_t base, uint32_t pin, uint8_t func)
+static void _quark_d2000_set_mux(uint32_t base, uint32_t pin, uint8_t func)
 {
 	/*
 	 * The register is a single 32-bit value, with CONFIG_PINMUX_NUM_PINS
@@ -144,24 +143,7 @@ static void _quark_d2000_pullup_set(uint32_t base, uint32_t pin, uint8_t func)
 	uint32_t enable_mask =  (func & 0x01) << pin;
 	uint32_t pin_mask = 0x1 << pin;
 
-	volatile uint32_t *mux_register =
-		(uint32_t *)(base + PINMUX_PULLUP_OFFSET);
-
-	(*(mux_register)) = (((*(mux_register)) & ~pin_mask) | enable_mask);
-}
-
-static void _quark_d2000_input_enable(uint32_t base, uint32_t pin, uint8_t func)
-{
-	/*
-	 * The register is a single 32-bit value, with CONFIG_PINMUX_NUM_PINS
-	 * bits set in it.  Each bit represents the input enable status of the
-	 * pin.
-	 */
-	uint32_t enable_mask =  (func & 0x01) << pin;
-	uint32_t pin_mask = 0x1 << pin;
-
-	volatile uint32_t *mux_register =
-		(uint32_t *)(base + PINMUX_INPUT_ENABLE_OFFSET);
+	volatile uint32_t *mux_register = (uint32_t *)(base);
 
 	(*(mux_register)) = (((*(mux_register)) & ~pin_mask) | enable_mask);
 }
@@ -264,7 +246,8 @@ static uint32_t pinmux_pullup_set(struct device *dev, uint32_t pin,
 {
 	struct pinmux_config * const pmux = dev->config->config_info;
 
-	_quark_d2000_pullup_set(pmux->base_address, pin, func);
+	_quark_d2000_set_mux(pmux->base_address + PINMUX_PULLUP_OFFSET, pin,
+			     func);
 
 	return DEV_OK;
 }
@@ -274,7 +257,8 @@ static uint32_t pinmux_input_enable(struct device *dev, uint32_t pin,
 {
 	struct pinmux_config * const pmux = dev->config->config_info;
 
-	_quark_d2000_input_enable(pmux->base_address, pin, func);
+	_quark_d2000_set_mux(pmux->base_address + PINMUX_INPUT_OFFSET, pin,
+			     func);
 
 	return DEV_OK;
 }
@@ -295,7 +279,7 @@ int pinmux_initialize(struct device *port)
 	_pinmux_defaults(pmux->base_address);
 
 	/* Enable the UART RX pin to receive input */
-	_quark_d2000_input_enable(pmux->base_address, 5, PINMUX_INPUT_ENABLED);
+	_quark_d2000_set_mux(pmux->base_address + PINMUX_INPUT_OFFSET, 5, 0x1);
 
 	return DEV_OK;
 }
diff --git a/boards/quark_se_ctb/pinmux.c b/boards/quark_se_ctb/pinmux.c
index cb7dd8fe566..0da3ba20f15 100644
--- a/boards/quark_se_ctb/pinmux.c
+++ b/boards/quark_se_ctb/pinmux.c
@@ -183,7 +183,7 @@ static void _pinmux_defaults(uint32_t base)
 
 static inline void _pinmux_pullups(uint32_t base_address) { };
 
-static uint32_t _quark_se_pullup(uint32_t base, uint32_t pin, uint8_t func)
+static uint32_t _quark_se_set_mux(uint32_t base, uint32_t pin, uint8_t func)
 {
 	/*
 	 * the registers are 32-bit wide, but each pin requires 1 bit
@@ -193,40 +193,8 @@ static uint32_t _quark_se_pullup(uint32_t base, uint32_t pin, uint8_t func)
 	/*
 	 * Now figure out what is the full address for the register
 	 * we are looking for.  Add the base register to the register_mask
-	 * Valid values include: 0x900, 0x904, 0x908, and 0x90C
 	 */
-	volatile uint32_t *mux_register =
-		(uint32_t *)(base + PINMUX_PULLUP_OFFSET + register_offset);
-
-	/*
-	 * Finally grab the pin offset within the register
-	 */
-	uint32_t pin_offset = pin % 32;
-
-	/*
-	 * MAGIC NUMBER: 0x1 is used as the pullup is a single bit in a
-	 * 32-bit register.
-	 */
-	(*(mux_register)) = ((*(mux_register)) & ~(0x1 << pin_offset)) |
-		(func << pin_offset);
-
-	return DEV_OK;
-}
-
-static uint32_t _quark_se_input(uint32_t base, uint32_t pin, uint8_t func)
-{
-	/*
-	 * the registers are 32-bit wide, but each pin requires 1 bit
-	 * to set the input enable bit.
-	 */
-	uint32_t register_offset = (pin / 32) * 4;
-	/*
-	 * Now figure out what is the full address for the register
-	 * we are looking for.  Add the base register to the register_mask
-	 * Valid values include: 0x920, 0x924, 0x928, and 0x92C
-	 */
-	volatile uint32_t *mux_register =
-		(uint32_t *)(base + PINMUX_INPUT_OFFSET + register_offset);
+	volatile uint32_t *mux_register = (uint32_t *)(base + register_offset);
 
 	/*
 	 * Finally grab the pin offset within the register
@@ -341,7 +309,7 @@ static uint32_t pinmux_dev_pullup(struct device *dev,
 {
 	const struct pinmux_config *pmux = dev->config->config_info;
 
-	_quark_se_pullup(pmux->base_address, pin, func);
+	_quark_se_set_mux(pmux->base_address + PINMUX_PULLUP_OFFSET, pin, func);
 
 	return DEV_OK;
 }
@@ -349,7 +317,7 @@ static uint32_t pinmux_dev_input(struct device *dev, uint32_t pin, uint8_t func)
 {
 	const struct pinmux_config *pmux = dev->config->config_info;
 
-	_quark_se_input(pmux->base_address, pin, func);
+	_quark_se_set_mux(pmux->base_address + PINMUX_INPUT_OFFSET, pin, func);
 
 	return DEV_OK;
 }