From ea42995f2ea2c3de5662d8560fdb9bba0652bbc0 Mon Sep 17 00:00:00 2001 From: Conor Paxton Date: Fri, 9 Jun 2023 21:59:05 +0100 Subject: [PATCH] dts: riscv: introduce PolarFire SoC I2C interface Add support for Microchip's PolarFire SoC I2C interface Signed-off-by: Conor Paxton --- dts/bindings/i2c/microchip,mpfs-i2c.yaml | 25 ++++++++++++++++++++++++ dts/riscv/microchip/mpfs-icicle.dtsi | 22 +++++++++++++++++++++ 2 files changed, 47 insertions(+) create mode 100644 dts/bindings/i2c/microchip,mpfs-i2c.yaml diff --git a/dts/bindings/i2c/microchip,mpfs-i2c.yaml b/dts/bindings/i2c/microchip,mpfs-i2c.yaml new file mode 100644 index 00000000000..36d0b00b7d8 --- /dev/null +++ b/dts/bindings/i2c/microchip,mpfs-i2c.yaml @@ -0,0 +1,25 @@ +# +# Copyright (c) 2023 Microchip Technology Inc. +# +# SPDX-License-Identifier: Apache-2.0 +# + +description: + Microchip MPFS I2C Controller Device Tree Bindings + +compatible: "microchip,mpfs-i2c" + +include: i2c-controller.yaml + +properties: + reg: + required: true + + interrupts: + required: true + + clock-frequency: + description: | + Desired I2C bus clock frequency in Hz. As only Standard and Fast + modes are supported, possible values are 100000 and 400000. + enum: [100000, 400000] diff --git a/dts/riscv/microchip/mpfs-icicle.dtsi b/dts/riscv/microchip/mpfs-icicle.dtsi index 5b130413f63..9c1d25161b5 100644 --- a/dts/riscv/microchip/mpfs-icicle.dtsi +++ b/dts/riscv/microchip/mpfs-icicle.dtsi @@ -233,5 +233,27 @@ ngpios = <32>; status = "disabled"; }; + + i2c0: i2c@2010a000 { + compatible = "microchip,mpfs-i2c"; + reg = <0x2010a000 0x1000>; + interrupt-parent = <&plic>; + interrupts = <58 1>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + status = "disabled"; + }; + + i2c1: i2c@2010b000 { + compatible = "microchip,mpfs-i2c"; + reg = <0x2010b000 0x1000>; + interrupt-parent = <&plic>; + interrupts = <61 1>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + status = "disabled"; + }; }; };