From e3f9293fc26408ee9eabefa9d2ce5bbd39a668c8 Mon Sep 17 00:00:00 2001
From: Francois Ramu <francois.ramu@st.com>
Date: Tue, 23 Jul 2024 09:42:42 +0200
Subject: [PATCH] dts: arm: stm32u59x serie with OTG HS instance

Add the USB OTG HS node for the stm32U59x/5Ax/5Fx/5Gx devices

Signed-off-by: Francois Ramu <francois.ramu@st.com>
---
 dts/arm/st/u5/stm32u595.dtsi | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/dts/arm/st/u5/stm32u595.dtsi b/dts/arm/st/u5/stm32u595.dtsi
index 3bc16eb120e..00147808da6 100644
--- a/dts/arm/st/u5/stm32u595.dtsi
+++ b/dts/arm/st/u5/stm32u595.dtsi
@@ -96,6 +96,26 @@
 			st,adc-clock-source = <ASYNC>;
 			st,adc-sequencer = <FULLY_CONFIGURABLE>;
 		};
+
+		usbotg_hs: otghs@42040000 {
+			compatible = "st,stm32-otghs";
+			reg = <0x42040000 0x20000>;
+			interrupts = <73 0>;
+			interrupt-names = "otghs";
+			num-bidir-endpoints = <9>;
+			ram-size = <4096>;
+			maximum-speed = "high-speed";
+			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x0000c000>,
+				 <&rcc STM32_SRC_HSI48 ICKLK_SEL(0)>;
+			phys = <&otghs_phy>;
+			status = "disabled";
+		};
+	};
+
+	otghs_phy: otghs_phy {
+		/* Clock source defined by USBPHYC_SEL in */
+		compatible = "usb-nop-xceiv";
+		#phy-cells = <0>;
 	};
 
 	smbus5: smbus5 {