From d3cd0d2f9aefb529f86d0bbad3e07fb985e91b4c Mon Sep 17 00:00:00 2001 From: David Leach Date: Thu, 19 Aug 2021 16:07:40 -0500 Subject: [PATCH] drivers: adc: add LPADC driver support to mimxrt685 platform Add LPADC support to the mimxrt685 platform. Signed-off-by: David Leach --- boards/arm/mimxrt685_evk/doc/index.rst | 2 + .../arm/mimxrt685_evk/mimxrt685_evk_cm33.dts | 4 + boards/arm/mimxrt685_evk/pinmux.c | 87 +++++++++++++++++++ drivers/adc/adc_mcux_lpadc.c | 14 ++- dts/arm/nxp/nxp_rt6xx_common.dtsi | 16 ++++ .../adc/boards/mimxrt685_evk_cm33.overlay | 12 +++ .../nxp_imx/rt6xx/Kconfig.defconfig.series | 4 + soc/arm/nxp_imx/rt6xx/Kconfig.soc | 1 + tests/drivers/adc/adc_api/src/test_adc.c | 3 +- west.yml | 2 +- 10 files changed, 142 insertions(+), 3 deletions(-) create mode 100644 samples/drivers/adc/boards/mimxrt685_evk_cm33.overlay diff --git a/boards/arm/mimxrt685_evk/doc/index.rst b/boards/arm/mimxrt685_evk/doc/index.rst index 5e04df35d6b..0ff480b4294 100644 --- a/boards/arm/mimxrt685_evk/doc/index.rst +++ b/boards/arm/mimxrt685_evk/doc/index.rst @@ -95,6 +95,8 @@ features: +-----------+------------+-------------------------------------+ | USB | on-chip | USB device | +-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ The default configuration can be found in the defconfig file: diff --git a/boards/arm/mimxrt685_evk/mimxrt685_evk_cm33.dts b/boards/arm/mimxrt685_evk/mimxrt685_evk_cm33.dts index cf0ef02ea71..09413fbc0fe 100644 --- a/boards/arm/mimxrt685_evk/mimxrt685_evk_cm33.dts +++ b/boards/arm/mimxrt685_evk/mimxrt685_evk_cm33.dts @@ -303,6 +303,10 @@ i2s1: &flexcomm3 { pwr-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; }; +&lpadc0 { + status = "okay"; +}; + zephyr_udc0: &usbhs { status = "okay"; }; diff --git a/boards/arm/mimxrt685_evk/pinmux.c b/boards/arm/mimxrt685_evk/pinmux.c index a5df9a469de..b45009f30bb 100644 --- a/boards/arm/mimxrt685_evk/pinmux.c +++ b/boards/arm/mimxrt685_evk/pinmux.c @@ -961,6 +961,93 @@ static int mimxrt685_evk_pinmux_init(const struct device *dev) IOPCTL_PinMuxSet(IOPCTL, 2U, 9U, port2_pin9_config); #endif +#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpadc0), okay) && CONFIG_ADC + /* + * The current test and sample applications uses a single channel for + * testing so we only need to enable the pin for that single use. + * + * If your application requires more then the mappings are as follows + * for the rt685_evk: + * + * +---------+------+---------+-------+ + * | Port# | ADC |Schematic|Arduino| + * | pin | Chn# | |header | + * +---------+------+---------+-------+ + * | PIO0_5 | CH0A | ADC0_0 | J30.1 | + * +---------+------+---------+-------+ + * | PIO0_6 | CH0B | ADC0_8 | J30.2 | + * +---------+------+---------+-------+ + * | PIO0_12 | CH1A | ADC0_1 | | + * +---------+------+---------+-------+ + * | PIO0_13 | CH1B | ADC0_9 | | + * +---------+------+---------+-------+ + * | PIO0_19 | CH2A | ADC0_2 | J30.3 | + * +---------+------+---------+-------+ + * | PIO0_20 | CH2B | ADC0_10 | J30.4 | + * +---------+------+---------+-------+ + * | PIO0_26 | CH3A | ADC0_3 | | + * +---------+------+---------+-------+ + * | PIO0_27 | CH3B | ADC0_11 | | + * +---------+------+---------+-------+ + * | PIO1_8 | CH4A | ADC0_4 | | + * +---------+------+---------+-------+ + * | PIO1_9 | CH4B | ADC0_12 | | + * +---------+------+---------+-------+ + * | PIO3_23 | CH5A | ADC0_5 | | + * +---------+------+---------+-------+ + * | PIO3_24 | CH5B | ADC0_13 | | + * +---------+------+---------+-------+ + * + * Per the mimxrt6xx reference manual, The channels 0-5 are analong input. + * Optionally, channels 0A through 5A can be paired with channels 0B + * through 5B for differential input on their respective ADC channel. + * + */ + const uint32_t port0_pin5_config = ( + /* Pin is configured as ADC0_0 */ + IOPCTL_PIO_FUNC0 | + /* Disable pull-up / pull-down function */ + IOPCTL_PIO_PUPD_DI | + /* Enable pull-down function */ + IOPCTL_PIO_PULLDOWN_EN | + /* Disable input buffer function */ + IOPCTL_PIO_INBUF_DI | + /* Normal mode */ + IOPCTL_PIO_SLEW_RATE_NORMAL | + /* Normal drive */ + IOPCTL_PIO_FULLDRIVE_DI | + /* Analog mux is enabled */ + IOPCTL_PIO_ANAMUX_EN | + /* Pseudo Output Drain is disabled */ + IOPCTL_PIO_PSEDRAIN_DI | + /* Input function is not inverted */ + IOPCTL_PIO_INV_DI); + /* PORT0 PIN5 (coords: F4) is configured as ADC0_0 */ + IOPCTL_PinMuxSet(IOPCTL, 0U, 5U, port0_pin5_config); + + const uint32_t port0_pin6_config = ( + /* Pin is configured as ADC0_8 */ + IOPCTL_PIO_FUNC0 | + /* Disable pull-up / pull-down function */ + IOPCTL_PIO_PUPD_DI | + /* Enable pull-down function */ + IOPCTL_PIO_PULLDOWN_EN | + /* Disable input buffer function */ + IOPCTL_PIO_INBUF_DI | + /* Normal mode */ + IOPCTL_PIO_SLEW_RATE_NORMAL | + /* Normal drive */ + IOPCTL_PIO_FULLDRIVE_DI | + /* Analog mux is enabled */ + IOPCTL_PIO_ANAMUX_EN | + /* Pseudo Output Drain is disabled */ + IOPCTL_PIO_PSEDRAIN_DI | + /* Input function is not inverted */ + IOPCTL_PIO_INV_DI); + /* PORT0 PIN6 (coords: E1) is configured as ADC0_8 */ + IOPCTL_PinMuxSet(IOPCTL, 0U, 6U, port0_pin6_config); +#endif + return 0; } diff --git a/drivers/adc/adc_mcux_lpadc.c b/drivers/adc/adc_mcux_lpadc.c index c04b6cecbf6..5cc485eb11e 100644 --- a/drivers/adc/adc_mcux_lpadc.c +++ b/drivers/adc/adc_mcux_lpadc.c @@ -273,11 +273,23 @@ static int mcux_lpadc_init(const struct device *dev) lpadc_config_t adc_config; #if !defined(CONFIG_SOC_SERIES_IMX_RT11XX) +#if defined(CONFIG_SOC_SERIES_IMX_RT6XX) + + SYSCTL0->PDRUNCFG0_CLR = SYSCTL0_PDRUNCFG0_ADC_PD_MASK; + SYSCTL0->PDRUNCFG0_CLR = SYSCTL0_PDRUNCFG0_ADC_LP_MASK; + RESET_PeripheralReset(kADC0_RST_SHIFT_RSTn); + CLOCK_AttachClk(kSFRO_to_ADC_CLK); + CLOCK_SetClkDiv(kCLOCK_DivAdcClk, config->clock_div); + +#else + CLOCK_SetClkDiv(kCLOCK_DivAdcAsyncClk, config->clock_div, true); CLOCK_AttachClk(config->clock_source); /* Power up the ADC */ POWER_DisablePD(kPDRUNCFG_PD_LDOGPADC); + +#endif #endif LPADC_GetDefaultConfig(&adc_config); @@ -357,7 +369,7 @@ static const struct adc_driver_api mcux_lpadc_driver_api = { #define ASSERT_WITHIN_RANGE(val, min, max, str) \ BUILD_ASSERT(val >= min && val <= max, str) -#if defined(CONFIG_SOC_SERIES_IMX_RT11XX) +#if defined(CONFIG_SOC_SERIES_IMX_RT11XX) || defined(CONFIG_SOC_SERIES_IMX_RT6XX) #define TO_LPADC_CLOCK_SOURCE(val) 0 #else #define TO_LPADC_CLOCK_SOURCE(val) \ diff --git a/dts/arm/nxp/nxp_rt6xx_common.dtsi b/dts/arm/nxp/nxp_rt6xx_common.dtsi index 92a5ffe1738..d6a41a40d3e 100644 --- a/dts/arm/nxp/nxp_rt6xx_common.dtsi +++ b/dts/arm/nxp/nxp_rt6xx_common.dtsi @@ -310,6 +310,22 @@ clocks = <&clkctl1 MCUX_USDHC2_CLK>; label = "USDHC_2"; }; + + lpadc0: lpadc@13A0000 { + compatible = "nxp,lpc-lpadc"; + reg = <0x13A000 0x304>; + interrupts = <22 0>; + status = "disabled"; + clk-divider = <1>; + clk-source = <0>; + voltage-ref= <2>; + calibration-average = <128>; + power-level = <1>; + label = "LPADC_0"; + offset-value-a = <10>; + offset-value-b = <10>; + #io-channel-cells = <1>; + }; }; &nvic { diff --git a/samples/drivers/adc/boards/mimxrt685_evk_cm33.overlay b/samples/drivers/adc/boards/mimxrt685_evk_cm33.overlay new file mode 100644 index 00000000000..c16048f63ae --- /dev/null +++ b/samples/drivers/adc/boards/mimxrt685_evk_cm33.overlay @@ -0,0 +1,12 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright (c) 2020 Linaro Limited + */ + +/ { + zephyr,user { + /* adjust channel number according to pinmux in board.dts */ + io-channels = <&lpadc0 0>; + }; +}; diff --git a/soc/arm/nxp_imx/rt6xx/Kconfig.defconfig.series b/soc/arm/nxp_imx/rt6xx/Kconfig.defconfig.series index 5f9169325f8..872d4c27c0f 100644 --- a/soc/arm/nxp_imx/rt6xx/Kconfig.defconfig.series +++ b/soc/arm/nxp_imx/rt6xx/Kconfig.defconfig.series @@ -27,6 +27,10 @@ config ENTROPY_MCUX_TRNG default y if HAS_MCUX_TRNG depends on ENTROPY_GENERATOR +config ADC_MCUX_LPADC + default y if HAS_MCUX_LPADC + depends on ADC + # # MBEDTLS is larger but much faster than TinyCrypt so choose wisely # diff --git a/soc/arm/nxp_imx/rt6xx/Kconfig.soc b/soc/arm/nxp_imx/rt6xx/Kconfig.soc index 5e836d6964a..b99624ac1a9 100644 --- a/soc/arm/nxp_imx/rt6xx/Kconfig.soc +++ b/soc/arm/nxp_imx/rt6xx/Kconfig.soc @@ -21,6 +21,7 @@ config SOC_MIMXRT685S_CM33 select HAS_MCUX_FLEXSPI select HAS_MCUX_CACHE select HAS_MCUX_LPC_DMA + select HAS_MCUX_LPADC select HAS_MCUX_OS_TIMER select HAS_MCUX_LPC_RTC select HAS_MCUX_TRNG diff --git a/tests/drivers/adc/adc_api/src/test_adc.c b/tests/drivers/adc/adc_api/src/test_adc.c index 98ed1d40c45..7e5291988a2 100644 --- a/tests/drivers/adc/adc_api/src/test_adc.c +++ b/tests/drivers/adc/adc_api/src/test_adc.c @@ -256,7 +256,8 @@ #elif defined(CONFIG_BOARD_LPCXPRESSO55S69_CPU0) || \ defined(CONFIG_BOARD_LPCXPRESSO55S28) || \ - defined(CONFIG_BOARD_MIMXRT1170_EVK_CM7) + defined(CONFIG_BOARD_MIMXRT1170_EVK_CM7) || \ + defined(CONFIG_BOARD_MIMXRT685_EVK) #define ADC_DEVICE_NAME DT_LABEL(DT_INST(0, nxp_lpc_lpadc)) #define ADC_RESOLUTION 12 #define ADC_GAIN ADC_GAIN_1 diff --git a/west.yml b/west.yml index b53a3a7d52e..4465c5272cc 100644 --- a/west.yml +++ b/west.yml @@ -88,7 +88,7 @@ manifest: groups: - hal - name: hal_nxp - revision: 6287a073922a42685cc0b63b97d35b49b66b7a8f + revision: 38e443d055afcdfe5306103d740ae10d4bf77e5b path: modules/hal/nxp groups: - hal