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arch: arm: cortex_a_r: Fix mrc/mcr instruction usage

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The coprocessor number in ARM `mrc` and `mcr` instructions must be prefixed
with `p`.

GNU assembler allows specifying coprocessor number without the `p` prefix;
but, LLVM assembler is more picky about this and prints out "invalid
instruction" error otherwise.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This commit is contained in:
Stephanos Ioannidis 2024-10-25 22:14:32 +09:00 committed by Dan Kalowsky
parent adced0c29b
commit cd9ddc95a8
2 changed files with 2 additions and 2 deletions
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2
arch/arm/core/cortex_a_r/__aeabi_read_tp.S
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@ -14,5 +14,5 @@ SECTION_FUNC(text, __aeabi_read_tp)
/*
* TPIDRURW will be used as a base pointer point to TLS aera.
*/
mrc 15, 0, r0, c13, c0, 2
mrc p15, 0, r0, c13, c0, 2
bx lr

2
arch/arm/core/cortex_a_r/swap_helper.S
View File

@ -126,7 +126,7 @@ out_fp_inactive:
* TPIDRURW is used as a base pointer to all
* thread variables with offsets added by toolchain.
*/
mcr 15, 0, r0, c13, c0, 2
mcr p15, 0, r0, c13, c0, 2
#endif
#if defined(CONFIG_ARM_STORE_EXC_RETURN)