From cb677febb14296d30eeb0b685cb145310fb53e39 Mon Sep 17 00:00:00 2001
From: Mateusz Holenko <mholenko@antmicro.com>
Date: Mon, 11 Dec 2023 18:17:51 +0100
Subject: [PATCH] dts: riscv: Fix a typo in riscv,isa for mpfs
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The RISC-V ISA extension is called `Zifencei` instead of `Zfencei`.

Signed-off-by: Mateusz Hołenko <mholenko@antmicro.com>
---
 dts/riscv/microchip/mpfs.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/dts/riscv/microchip/mpfs.dtsi b/dts/riscv/microchip/mpfs.dtsi
index e0d206789db..6b81720e095 100644
--- a/dts/riscv/microchip/mpfs.dtsi
+++ b/dts/riscv/microchip/mpfs.dtsi
@@ -19,7 +19,7 @@
 			compatible = "riscv";
 			device_type = "cpu";
 			reg = < 0x0 >;
-			riscv,isa = "rv64imac_zicsr_zfencei";
+			riscv,isa = "rv64imac_zicsr_zifencei";
 			hlic0: interrupt-controller {
 				compatible = "riscv,cpu-intc";
 				#address-cells = <0>;