From ca8ee0e029802afc44fbd85594dfcb5ed240bcff Mon Sep 17 00:00:00 2001 From: Aaron Ye Date: Thu, 11 Jan 2024 11:37:52 +0800 Subject: [PATCH] boards: arm: apollo4p_blue_kxr_evb: Move the bt-spi instance to soc dts Since the pins of bt-spi instance are wired internally in the chip, it will make sense to move the definition to soc dts so no need for every board using the chip to redefine the same. Signed-off-by: Aaron Ye --- .../apollo4p_blue_kxr_evb.dts | 11 ----------- dts/arm/ambiq/ambiq_apollo4p_blue.dtsi | 14 +++++++++++++- 2 files changed, 13 insertions(+), 12 deletions(-) diff --git a/boards/arm/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb.dts b/boards/arm/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb.dts index cb4014a4f08..f9aa3c11c31 100644 --- a/boards/arm/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb.dts +++ b/boards/arm/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb.dts @@ -87,20 +87,9 @@ }; &iom4 { - compatible = "ambiq,spi"; pinctrl-0 = <&spi4_default>; pinctrl-names = "default"; - cs-gpios = <&gpio32_63 22 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - clock-frequency = ; status = "okay"; - - bt-hci@0 { - compatible = "ambiq,bt-hci-spi"; - reg = <0>; - irq-gpios = <&gpio32_63 21 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio32_63 23 GPIO_ACTIVE_LOW>; - clkreq-gpios = <&gpio32_63 20 GPIO_ACTIVE_HIGH>; - }; }; &mspi0 { diff --git a/dts/arm/ambiq/ambiq_apollo4p_blue.dtsi b/dts/arm/ambiq/ambiq_apollo4p_blue.dtsi index 5df5c7d4b47..dfc2f59de3d 100644 --- a/dts/arm/ambiq/ambiq_apollo4p_blue.dtsi +++ b/dts/arm/ambiq/ambiq_apollo4p_blue.dtsi @@ -160,13 +160,25 @@ ambiq,pwrcfg = <&pwrcfg 0x4 0x10>; }; - iom4: iom@40054000 { + iom4: spi@40054000 { + /* IOM4 works as SPI and is wired internally for BLE HCI. */ + compatible = "ambiq,spi"; reg = <0x40054000 0x1000>; #address-cells = <1>; #size-cells = <0>; interrupts = <10 0>; + cs-gpios = <&gpio32_63 22 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + clock-frequency = ; status = "disabled"; ambiq,pwrcfg = <&pwrcfg 0x4 0x20>; + + bt-hci@0 { + compatible = "ambiq,bt-hci-spi"; + reg = <0>; + irq-gpios = <&gpio32_63 21 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio32_63 23 GPIO_ACTIVE_LOW>; + clkreq-gpios = <&gpio32_63 20 GPIO_ACTIVE_HIGH>; + }; }; iom5: iom@40055000 {