From c084c0e77644aa70c07df3c34f8ea35f79b1c98f Mon Sep 17 00:00:00 2001
From: Scott Worley <scott.worley@microchip.com>
Date: Wed, 23 Jul 2025 10:59:34 -0400
Subject: [PATCH] tests: arch: arm: arm_irq_vector_table: Microchip MEC build
 fix

Running twister with plaform Microchip mec_assy6941/<variant_name>
builds the arm_irq_vector_table test. Microchip mec_assy6941 boards
all use a 32-bit 32 KHz timer for the kernel. The test build fails
due to any board using a custom kernel timer driver requires the
test to include a chip specific interrupt table. We don't want to
exclude the test. The MEC chips include Cortex-M4 SysTick. We added
board overlays to the test turning off the 32KHz timer and enabling
ARM SysTick. The test now builds.

Signed-off-by: Scott Worley <scott.worley@microchip.com>
---
 .../boards/mec_assy6941_mec1743_qlj.overlay     | 17 +++++++++++++++++
 .../boards/mec_assy6941_mec1743_qsz.overlay     | 17 +++++++++++++++++
 .../boards/mec_assy6941_mec1753_qlj.overlay     | 17 +++++++++++++++++
 .../boards/mec_assy6941_mec1753_qsz.overlay     | 17 +++++++++++++++++
 4 files changed, 68 insertions(+)
 create mode 100644 tests/arch/arm/arm_irq_vector_table/boards/mec_assy6941_mec1743_qlj.overlay
 create mode 100644 tests/arch/arm/arm_irq_vector_table/boards/mec_assy6941_mec1743_qsz.overlay
 create mode 100644 tests/arch/arm/arm_irq_vector_table/boards/mec_assy6941_mec1753_qlj.overlay
 create mode 100644 tests/arch/arm/arm_irq_vector_table/boards/mec_assy6941_mec1753_qsz.overlay

diff --git a/tests/arch/arm/arm_irq_vector_table/boards/mec_assy6941_mec1743_qlj.overlay b/tests/arch/arm/arm_irq_vector_table/boards/mec_assy6941_mec1743_qlj.overlay
new file mode 100644
index 00000000000..7bd2a7bb72c
--- /dev/null
+++ b/tests/arch/arm/arm_irq_vector_table/boards/mec_assy6941_mec1743_qlj.overlay
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2025 Microchip Technology Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Microchip MEC use its 32 KHz based RTOS timer by default.
+ * Allow the test to build by switching to Cortex-M4 SysTick.
+ */
+
+&rtimer {
+	status = "disabled";
+};
+
+&systick {
+	status = "okay";
+};
diff --git a/tests/arch/arm/arm_irq_vector_table/boards/mec_assy6941_mec1743_qsz.overlay b/tests/arch/arm/arm_irq_vector_table/boards/mec_assy6941_mec1743_qsz.overlay
new file mode 100644
index 00000000000..7bd2a7bb72c
--- /dev/null
+++ b/tests/arch/arm/arm_irq_vector_table/boards/mec_assy6941_mec1743_qsz.overlay
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2025 Microchip Technology Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Microchip MEC use its 32 KHz based RTOS timer by default.
+ * Allow the test to build by switching to Cortex-M4 SysTick.
+ */
+
+&rtimer {
+	status = "disabled";
+};
+
+&systick {
+	status = "okay";
+};
diff --git a/tests/arch/arm/arm_irq_vector_table/boards/mec_assy6941_mec1753_qlj.overlay b/tests/arch/arm/arm_irq_vector_table/boards/mec_assy6941_mec1753_qlj.overlay
new file mode 100644
index 00000000000..7bd2a7bb72c
--- /dev/null
+++ b/tests/arch/arm/arm_irq_vector_table/boards/mec_assy6941_mec1753_qlj.overlay
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2025 Microchip Technology Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Microchip MEC use its 32 KHz based RTOS timer by default.
+ * Allow the test to build by switching to Cortex-M4 SysTick.
+ */
+
+&rtimer {
+	status = "disabled";
+};
+
+&systick {
+	status = "okay";
+};
diff --git a/tests/arch/arm/arm_irq_vector_table/boards/mec_assy6941_mec1753_qsz.overlay b/tests/arch/arm/arm_irq_vector_table/boards/mec_assy6941_mec1753_qsz.overlay
new file mode 100644
index 00000000000..7bd2a7bb72c
--- /dev/null
+++ b/tests/arch/arm/arm_irq_vector_table/boards/mec_assy6941_mec1753_qsz.overlay
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2025 Microchip Technology Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Microchip MEC use its 32 KHz based RTOS timer by default.
+ * Allow the test to build by switching to Cortex-M4 SysTick.
+ */
+
+&rtimer {
+	status = "disabled";
+};
+
+&systick {
+	status = "okay";
+};