From bfc2f784cef6b0eb797c610ad30fb924fa877d8a Mon Sep 17 00:00:00 2001 From: Alexander Kozhinov Date: Sun, 8 Dec 2024 20:22:58 +0100 Subject: [PATCH] mks_canable_v20: fix fdcan1 clock select Use STM32_CLOCK() clock select macro with bit-25 set. This change shall set register RCC_CCIPR->FDCANSEL to 0x01. Previosuly there were bit-12 set, which was wrong. For more information refer to RM0440 Rev. 8 page 323 of 2138. Signed-off-by: Alexander Kozhinov --- boards/makerbase/mks_canable_v20/mks_canable_v20.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/boards/makerbase/mks_canable_v20/mks_canable_v20.dts b/boards/makerbase/mks_canable_v20/mks_canable_v20.dts index b619d8b900c..2f2e54565f9 100644 --- a/boards/makerbase/mks_canable_v20/mks_canable_v20.dts +++ b/boards/makerbase/mks_canable_v20/mks_canable_v20.dts @@ -81,7 +81,7 @@ zephyr_udc0: &usb { &fdcan1 { pinctrl-0 = <&fdcan1_rx_pb8 &fdcan1_tx_pb9>; pinctrl-names = "default"; - clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00001000>, + clocks = <&rcc STM32_CLOCK(APB1, 25U)>, <&rcc STM32_SRC_PLL_Q FDCAN_SEL(1)>; status = "okay"; };