soc: riscv: andes_v5: refine Andes PMA
Refine PMA driver and define MPU_ALIGN() to PMA granularity in RAM_SECTIONS, otherwise MPU_ALIGN() is defined to PMP granularity. Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
This commit is contained in:
Jimmy Zheng
Fabio Baltieri
parent
de1cd06294
commit
bf0e01bee2
@ -57,22 +57,6 @@
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#define RAM_BASE CONFIG_SRAM_BASE_ADDRESS
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#define RAM_SIZE KB(CONFIG_SRAM_SIZE)
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/* Make linker section alignment comply with PMA granularity. */
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#if defined(CONFIG_SOC_ANDES_V5_PMA_REGION_MIN_ALIGN_AND_SIZE)
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_region_min_align = CONFIG_SOC_ANDES_V5_PMA_REGION_MIN_ALIGN_AND_SIZE;
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#else
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_region_min_align = 4;
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#endif
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#if defined(CONFIG_SOC_ANDES_V5_PMA)
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/*
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* Andes-V5 PMA needs power-of-2 alignment.
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*/
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#define MPU_MIN_SIZE_ALIGN . = ALIGN(_region_min_align);
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#define MPU_ALIGN(region_size) \
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. = ALIGN(_region_min_align); \
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. = ALIGN( 1 << LOG2CEIL(region_size))
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#else
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#ifdef CONFIG_RISCV_PMP
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#define MPU_MIN_SIZE CONFIG_PMP_GRANULARITY
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#define MPU_MIN_SIZE_ALIGN . = ALIGN(MPU_MIN_SIZE);
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@ -88,7 +72,6 @@ _region_min_align = 4;
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#define MPU_MIN_SIZE_ALIGN
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#define MPU_ALIGN(region_size) . = ALIGN(4)
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#endif
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#endif
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MEMORY
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{
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@ -214,11 +197,25 @@ SECTIONS
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. = RAM_BASE;
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_image_ram_start = .;
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#ifdef CONFIG_SOC_ANDES_V5_PMA
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#pragma push_macro("MPU_ALIGN")
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#undef MPU_ALIGN
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/* Make linker section alignment comply with PMA granularity. */
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#define MPU_ALIGN(region_size) \
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. = ALIGN(CONFIG_SOC_ANDES_V5_PMA_REGION_MIN_ALIGN_AND_SIZE); \
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. = ALIGN( 1 << LOG2CEIL(region_size))
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#endif
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/* Located in generated directory. This file is populated by the
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* zephyr_linker_sources() Cmake function.
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*/
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#include <snippets-ram-sections.ld>
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#ifdef CONFIG_SOC_ANDES_V5_PMA
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#pragma pop_macro("MPU_ALIGN")
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#endif
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#if defined(CONFIG_USERSPACE)
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#define APP_SHARED_ALIGN MPU_MIN_SIZE_ALIGN
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#define SMEM_PARTITION_ALIGN MPU_ALIGN
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@ -8,6 +8,7 @@
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#include <zephyr/kernel.h>
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#include <zephyr/arch/cpu.h>
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#include <zephyr/linker/linker-defs.h>
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#include <zephyr/arch/riscv/csr.h>
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#ifndef CONFIG_ASSERT
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#define LOG_LEVEL CONFIG_LOG_DEFAULT_LEVEL
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@ -16,14 +17,14 @@ LOG_MODULE_REGISTER(pma_init, LOG_LEVEL);
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#endif
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/* Programmable PMA mechanism is supported */
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#define MMSC_CFG_PPMA (1 << 30)
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#define MMSC_CFG_PPMA BIT(30)
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/*
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* PMA Configuration (PMACFG) bitfields
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*/
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/* ETYPE: Entry address matching mode */
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#define PMACFG_ETYPE_MASK 3
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#define PMACFG_ETYPE_MASK BIT_MASK(2)
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#define PMACFG_ETYPE_OFF 0
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#define PMACFG_ETYPE_TOR 1
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#define PMACFG_ETYPE_NA4 2
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@ -41,9 +42,7 @@ LOG_MODULE_REGISTER(pma_init, LOG_LEVEL);
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/* The base address is aligned to size */
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#define NAPOT_BASE(start, size) TO_PMA_ADDR((start) & ~((size) - 1))
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/* The encoding of size is 0b01...1
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* (change the leading bit of bitmask to 0)
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*/
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/* The encoding of size is 0b01...1, (change the leading bit of bitmask to 0) */
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#define NAPOT_SIZE(size) TO_PMA_ADDR(((size) - 1) >> 1)
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#define NA4_ENCODING(start) TO_PMA_ADDR(start)
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@ -58,12 +57,6 @@ LOG_MODULE_REGISTER(pma_init, LOG_LEVEL);
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#endif
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#define PMACFG_SHIFT(index) ((index % RV_REGSIZE) * 8)
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/* Wrappers of inline assembly */
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#define read_csr(var, csr) \
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({ __asm__ volatile ("csrr %0, %1" : "=r" (var) : "i" (csr)); })
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#define write_csr(csr, val) \
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({ __asm__ volatile ("csrw %0, %1" :: "i" (csr), "r" (val)); })
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struct pma_region_attr {
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/* Attributes belonging to pmacfg{i} */
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uint8_t pmacfg;
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@ -80,62 +73,32 @@ struct pma_region {
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*/
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static void write_pmaaddr_csr(const uint32_t index, unsigned long value)
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{
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#define SWITCH_CASE_PMAADDR_WRITE(x) \
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case (x): \
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csr_write(NDS_PMAADDR##x, value); break;
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switch (index) {
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case 0:
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write_csr(NDS_PMAADDR0, value); break;
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case 1:
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write_csr(NDS_PMAADDR1, value); break;
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case 2:
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write_csr(NDS_PMAADDR2, value); break;
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case 3:
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write_csr(NDS_PMAADDR3, value); break;
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case 4:
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write_csr(NDS_PMAADDR4, value); break;
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case 5:
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write_csr(NDS_PMAADDR5, value); break;
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case 6:
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write_csr(NDS_PMAADDR6, value); break;
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case 7:
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write_csr(NDS_PMAADDR7, value); break;
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case 8:
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write_csr(NDS_PMAADDR8, value); break;
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case 9:
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write_csr(NDS_PMAADDR9, value); break;
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case 10:
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write_csr(NDS_PMAADDR10, value); break;
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case 11:
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write_csr(NDS_PMAADDR11, value); break;
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case 12:
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write_csr(NDS_PMAADDR12, value); break;
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case 13:
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write_csr(NDS_PMAADDR13, value); break;
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case 14:
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write_csr(NDS_PMAADDR14, value); break;
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case 15:
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write_csr(NDS_PMAADDR15, value); break;
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FOR_EACH(SWITCH_CASE_PMAADDR_WRITE, (;), 0, 1, 2, 3, 4, 5, 6, 7,
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8, 9, 10, 11, 12, 13, 14, 15);
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}
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}
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/*
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* Write value to pma{i}cfg entry which are packed into CSRs pmacfg{j}
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*/
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static void write_pmacfg_entry(const uint32_t entry_index,
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uint8_t entry_value)
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static void write_pmacfg_entry(const uint32_t entry_index, uint8_t entry_value)
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{
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/* 1-byte pma{i}cfg entries are packed into XLEN-byte CSRs pmacfg{j} */
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uint32_t index = PMACFG_NUM(entry_index);
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uint8_t shift = PMACFG_SHIFT(entry_index);
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unsigned long pmacfg = 0;
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#define SWITCH_CASE_PMACFG_READ(x) \
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case (x): \
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pmacfg = csr_read(NDS_PMACFG##x); break;
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switch (index) {
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case 0:
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read_csr(pmacfg, NDS_PMACFG0); break;
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case 1:
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read_csr(pmacfg, NDS_PMACFG1); break;
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case 2:
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read_csr(pmacfg, NDS_PMACFG2); break;
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case 3:
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read_csr(pmacfg, NDS_PMACFG3); break;
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FOR_EACH(SWITCH_CASE_PMACFG_READ, (;), 0, 1, 2, 3);
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}
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/* clear old value in pmacfg entry */
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@ -143,15 +106,12 @@ static void write_pmacfg_entry(const uint32_t entry_index,
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/* set new value to pmacfg entry value */
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pmacfg |= entry_value << shift;
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#define SWITCH_CASE_PMACFG_WRITE(x) \
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case (x): \
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csr_write(NDS_PMACFG##x, pmacfg); break;
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switch (index) {
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case 0:
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write_csr(NDS_PMACFG0, pmacfg); break;
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case 1:
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write_csr(NDS_PMACFG1, pmacfg); break;
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case 2:
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write_csr(NDS_PMACFG2, pmacfg); break;
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case 3:
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write_csr(NDS_PMACFG3, pmacfg); break;
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FOR_EACH(SWITCH_CASE_PMACFG_WRITE, (;), 0, 1, 2, 3);
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}
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}
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@ -185,19 +145,18 @@ static void region_init(const uint32_t index,
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*/
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static int pma_region_is_valid(const struct pma_region *region)
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{
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/* Region size must be power-of-two,
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* and greater or equal to the minimum
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* PMA region size. Start address of the
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* region must align with size.
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*/
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int region_is_valid =
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((region->size & (region->size - 1)) == 0U)
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&&
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(region->size >= CONFIG_SOC_ANDES_V5_PMA_REGION_MIN_ALIGN_AND_SIZE)
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&&
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((region->start & (region->size - 1)) == 0U);
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/* Region size must greater or equal to the minimum PMA region size */
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if (region->size < CONFIG_SOC_ANDES_V5_PMA_REGION_MIN_ALIGN_AND_SIZE) {
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return -EINVAL;
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}
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if (!region_is_valid) {
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/* Region size must be power-of-two */
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if (region->size & (region->size - 1)) {
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return -EINVAL;
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}
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/* Start address of the region must align with size */
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if (region->start & (region->size - 1)) {
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return -EINVAL;
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}
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@ -213,11 +172,13 @@ static void configure_nocache_region(void)
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.attr = {PMACFG_MTYPE_MEMORY_NOCACHE_BUFFERABLE},
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};
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if (nocache_region.size != 0) {
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if (pma_region_is_valid(&nocache_region) == -EINVAL) {
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__ASSERT(0, "Configuring PMA region of nocache region failed\n");
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if (pma_region_is_valid(&nocache_region)) {
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/* Skip PMA configuration if nocache region size is 0 */
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if (nocache_region.size != 0) {
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__ASSERT(0, "Configuring PMA region of nocache region "
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"failed\n");
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}
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} else {
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/* Initialize nocache region at PMA region 0 */
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region_init(0, &nocache_region);
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}
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@ -242,7 +203,7 @@ static int pma_init(void)
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{
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unsigned long mmsc_cfg;
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__asm__ volatile ("csrr %0, %1" : "=r" (mmsc_cfg) : "i" (NDS_MMSC_CFG));
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mmsc_cfg = csr_read(NDS_MMSC_CFG);
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if (!(mmsc_cfg & MMSC_CFG_PPMA)) {
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/* This CPU doesn't support PMA */
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@ -250,7 +211,8 @@ static int pma_init(void)
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__ASSERT(0, "CPU doesn't support PMA. "
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"Please disable CONFIG_SOC_ANDES_V5_PMA\n");
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#ifndef CONFIG_ASSERT
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LOG_ERR("CPU doesn't support PMA. Please disable CONFIG_SOC_ANDES_V5_PMA");
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LOG_ERR("CPU doesn't support PMA. "
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"Please disable CONFIG_SOC_ANDES_V5_PMA");
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#endif
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return -ENODEV;
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}
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@ -260,5 +222,4 @@ static int pma_init(void)
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return 0;
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}
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SYS_INIT(pma_init, PRE_KERNEL_2,
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CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
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SYS_INIT(pma_init, PRE_KERNEL_2, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
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