soc: renesas: ra: Add support for Renesas RA8P1 SoC

Add support for Renesas RA8P1 SoC

Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>

soc/renesas/ra/ra8p1/CMakeLists.txt

@@ -0,0 +1,16 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories(.)
+
+zephyr_sources(
+  soc.c
+)
+
+zephyr_sources_ifdef(CONFIG_PM
+  power.c
+)
+
+zephyr_linker_sources(SECTIONS sections.ld)
+
+set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")

soc/renesas/ra/ra8p1/Kconfig

@@ -0,0 +1,25 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_RA8P1
+	select ARM
+	select CPU_HAS_ARM_SAU
+	select CPU_HAS_ARM_MPU
+	select CPU_HAS_FPU
+	select FPU
+	select CPU_CORTEX_M_HAS_SYSTICK
+	select CPU_CORTEX_M_HAS_DWT
+	select ARMV8_M_DSP
+	select HAS_SWO
+	select XIP
+	select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL
+	select HAS_RENESAS_RA_FSP
+	select SOC_EARLY_INIT_HOOK
+	select HAS_PM
+
+config SOC_R7KA8P1KFLCAC_CM85
+	select CPU_CORTEX_M85
+	select GPIO_RA_HAS_VBTICTLR
+
+config SOC_R7KA8P1KFLCAC_CM33
+	select CPU_CORTEX_M33

soc/renesas/ra/ra8p1/Kconfig.defconfig

@@ -0,0 +1,42 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_RA8P1
+
+config NUM_IRQS
+	default 96
+
+DT_CPUCLK0_PATH := $(dt_nodelabel_path,cpuclk0)
+DT_CPUCLK1_PATH := $(dt_nodelabel_path,cpuclk1)
+DT_LOCO_PATH := $(dt_nodelabel_path,loco)
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default $(dt_node_int_prop_int,$(DT_CPUCLK0_PATH),clock-frequency) if SOC_R7KA8P1KFLCAC_CM85 && CORTEX_M_SYSTICK
+	default $(dt_node_int_prop_int,$(DT_CPUCLK1_PATH),clock-frequency) if SOC_R7KA8P1KFLCAC_CM33 && CORTEX_M_SYSTICK
+	default $(dt_node_int_prop_int,$(DT_LOCO_PATH),clock-frequency) if RENESAS_RA_ULPT_TIMER
+
+config CORTEX_M_SYSTICK
+	default n if RENESAS_RA_ULPT_TIMER
+
+config SYS_CLOCK_TICKS_PER_SEC
+	default 4096 if RENESAS_RA_ULPT_TIMER
+
+config PM_DEVICE
+	default y if PM
+
+config PM_STATS
+	default n if PM
+
+config BUILD_OUTPUT_HEX
+	default y
+
+config CLOCK_CONTROL
+	default y
+
+config DCACHE
+	default n
+
+config CACHE_MANAGEMENT
+	default n
+
+endif # SOC_SERIES_RA8P1

soc/renesas/ra/ra8p1/Kconfig.soc

@@ -0,0 +1,28 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_RA8P1
+	bool
+	select SOC_FAMILY_RENESAS_RA
+	help
+	  Renesas RA8P1 series
+
+config SOC_R7KA8P1KFLCAC
+	bool
+	select SOC_SERIES_RA8P1
+	help
+	  R7KA8P1KFLCAC
+
+config SOC_R7KA8P1KFLCAC_CM85
+	bool
+	select SOC_R7KA8P1KFLCAC
+
+config SOC_R7KA8P1KFLCAC_CM33
+	bool
+	select SOC_R7KA8P1KFLCAC
+
+config SOC_SERIES
+	default "ra8p1" if SOC_SERIES_RA8P1
+
+config SOC
+	default "r7ka8p1kflcac" if SOC_R7KA8P1KFLCAC

soc/renesas/ra/ra8p1/power.c

@@ -0,0 +1,96 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/pm/pm.h>
+#include <zephyr/init.h>
+#include <soc.h>
+#include <r_lpm.h>
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_DECLARE(soc, CONFIG_SOC_LOG_LEVEL);
+
+/* Low Power Mode instance control structure */
+static lpm_instance_ctrl_t pm_state_ctrl;
+
+/* Configuration for Runtime Idle Power State */
+const lpm_cfg_t pm_state_runtime_idle_cfg = {
+	.low_power_mode = LPM_MODE_SLEEP,
+	.standby_wake_sources = LPM_STANDBY_WAKE_SOURCE_ULP0U,
+	.output_port_enable = LPM_OUTPUT_PORT_ENABLE_RETAIN,
+	.io_port_state = LPM_IO_PORT_NO_CHANGE,
+	.power_supply_state = LPM_POWER_SUPPLY_DEEP_STANDBY_MODE1,
+	.deep_standby_cancel_source = (lpm_deep_standby_cancel_source_t)0,
+	.deep_standby_cancel_edge = (lpm_deep_standby_cancel_edge_t)0,
+	.ram_retention_cfg.ram_retention = (uint16_t)(0x7F),
+	.ram_retention_cfg.tcm_retention = true,
+	.ldo_standby_cfg.pll1_ldo = false,
+	.ldo_standby_cfg.pll2_ldo = false,
+	.ldo_standby_cfg.hoco_ldo = false,
+	.p_extend = NULL,
+};
+
+/* Configuration for Standby Power State */
+const lpm_cfg_t pm_state_standby_cfg = {
+	.low_power_mode = LPM_MODE_STANDBY,
+	.standby_wake_sources = LPM_STANDBY_WAKE_SOURCE_ULP0U,
+	.output_port_enable = LPM_OUTPUT_PORT_ENABLE_RETAIN,
+	.io_port_state = LPM_IO_PORT_NO_CHANGE,
+	.power_supply_state = LPM_POWER_SUPPLY_DEEP_STANDBY_MODE1,
+	.deep_standby_cancel_source = (lpm_deep_standby_cancel_source_t)0,
+	.deep_standby_cancel_edge = (lpm_deep_standby_cancel_edge_t)0,
+	.ram_retention_cfg.ram_retention = (uint16_t)(0x7F),
+	.ram_retention_cfg.tcm_retention = true,
+	.ldo_standby_cfg.pll1_ldo = false,
+	.ldo_standby_cfg.pll2_ldo = false,
+	.ldo_standby_cfg.hoco_ldo = false,
+	.p_extend = NULL,
+};
+
+void pm_state_set(enum pm_state state, uint8_t substate_id)
+{
+	switch (state) {
+	case PM_STATE_RUNTIME_IDLE:
+		R_LPM_Open(&pm_state_ctrl, &pm_state_runtime_idle_cfg);
+		__disable_irq();
+		__set_BASEPRI(0);
+		__ISB();
+
+		R_LPM_LowPowerModeEnter(&pm_state_ctrl);
+		__enable_irq();
+		__ISB();
+		break;
+
+	case PM_STATE_STANDBY:
+		R_LPM_Open(&pm_state_ctrl, &pm_state_standby_cfg);
+		__disable_irq();
+		__set_BASEPRI(0);
+		__ISB();
+
+		R_LPM_LowPowerModeEnter(&pm_state_ctrl);
+		__enable_irq();
+		__ISB();
+		break;
+
+	default:
+		break;
+	}
+}
+
+void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
+{
+	switch (state) {
+	case PM_STATE_RUNTIME_IDLE:
+		__fallthrough;
+	case PM_STATE_STANDBY:
+		R_LPM_Close(&pm_state_ctrl);
+		break;
+
+	default:
+		break;
+	}
+	irq_unlock(0);
+}

soc/renesas/ra/ra8p1/sections.ld

@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),)
+{
+	/* If DTC is used, put the DTC vector table at the start of SRAM.
+		This avoids memory holes due to 1K alignment required by it. */
+	*(.fsp_dtc_vector_table)
+} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)

soc/renesas/ra/ra8p1/soc.c

@@ -0,0 +1,93 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief System/hardware module for Renesas RA8P1 family processor
+ */
+
+#include <zephyr/device.h>
+#include <zephyr/init.h>
+#include <zephyr/kernel.h>
+#include <zephyr/arch/cpu.h>
+#include <cmsis_core.h>
+#include <zephyr/irq.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/sys/barrier.h>
+#include <zephyr/cache.h>
+LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
+
+#include <bsp_api.h>
+
+#define CCR_CACHE_ENABLE (SCB_CCR_IC_Msk | SCB_CCR_BP_Msk | SCB_CCR_LOB_Msk)
+
+uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT;
+
+volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT;
+
+/**
+ * @brief Perform basic hardware initialization at boot.
+ *
+ * This needs to be run from the very beginning.
+ */
+void soc_early_init_hook(void)
+{
+	SystemCoreClock = BSP_MOCO_HZ;
+	g_protect_pfswe_counter = 0;
+
+	extern volatile uint16_t g_protect_counters[];
+
+	for (uint32_t i = 0; i < 4; i++) {
+		g_protect_counters[i] = 0;
+	}
+
+	SystemCoreClock = BSP_MOCO_HZ;
+
+#ifdef CONFIG_CPU_CORTEX_M85
+#ifdef CONFIG_ICACHE
+	SCB->CCR = (uint32_t)CCR_CACHE_ENABLE;
+	barrier_dsync_fence_full();
+	barrier_isync_fence_full();
+#endif
+#if defined(CONFIG_DCACHE) && defined(CONFIG_CACHE_MANAGEMENT)
+	/* Apply Arm Cortex-M85 errata workarounds for D-Cache
+	 * Attributing all cacheable memory as write-through set FORCEWT bit in MSCR register.
+	 * Set bit 16 in ACTLR to 1.
+	 * See erratum 3175626 and 3190818 in the Cortex-M85 AT640 and Cortex-M85 with FPU AT641
+	 * Software Developer Errata Notice (Date of issue: March 07, 2024, Document version: 13.0,
+	 * Document ID: SDEN-2236668).
+	 */
+	MEMSYSCTL->MSCR |= MEMSYSCTL_MSCR_FORCEWT_Msk;
+	barrier_dsync_fence_full();
+	barrier_isync_fence_full();
+	ICB->ACTLR |= (1U << 16U);
+	barrier_dsync_fence_full();
+	barrier_isync_fence_full();
+
+	sys_cache_data_enable();
+#endif
+#endif /*CONFIG_CPU_CORTEX_M85*/
+
+#ifdef CONFIG_CPU_CORTEX_M33
+#if FSP_PRIV_TZ_USE_SECURE_REGS
+	/* Disable protection using PRCR register. */
+	R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SAR);
+
+	/* Initialize peripherals to secure mode for flat projects */
+	R_PSCU->PSARB = 0;
+	R_PSCU->PSARC = 0;
+	R_PSCU->PSARD = 0;
+	R_PSCU->PSARE = 0;
+
+	R_CPSCU->ICUSARG = 0;
+	R_CPSCU->ICUSARH = 0;
+	R_CPSCU->ICUSARI = 0;
+
+	/* Enable protection using PRCR register. */
+	R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_SAR);
+#endif
+#endif /*CONFIG_CPU_CORTEX_M33*/
+}

soc/renesas/ra/ra8p1/soc.h

@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file SoC configuration macros for the Renesas RA8P1 family MCU
+ */
+
+#ifndef ZEPHYR_SOC_RENESAS_RA8P1_SOC_H_
+#define ZEPHYR_SOC_RENESAS_RA8P1_SOC_H_
+
+#include <bsp_api.h>
+
+#endif /* ZEPHYR_SOC_RENESAS_RA8P1_SOC_H_ */

soc/renesas/ra/soc.yml

@@ -70,3 +70,9 @@ family:
       - name: ra8t1
         socs:
           - name: r7fa8t1ahecbd
+      - name: ra8p1
+        socs:
+          - name: r7ka8p1kflcac
+            cpuclusters:
+              - name: cm85
+              - name: cm33