From b5d6f7f185ace0bd8dc0d394fcd78473abde0b19 Mon Sep 17 00:00:00 2001
From: Henrik Brix Andersen <henrik@brixandersen.dk>
Date: Mon, 23 Aug 2021 21:48:09 +0200
Subject: [PATCH] dts: riscv: neorv32: add gpio nodes

Add devicetree nodes for the NEORV32 GPIO device.

The GPIO port is 64 bits wide, but Zephyr only supports up to 32 bit
wide GPIO ports. The GPIO device is therefore handled as two Zephyr GPIO
devices with a nexus devicetree node mapping pins 0 to 31 to the device
handling the lower half, and pins 32 to 63 to the device handling the
upper half.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
---
 dts/riscv/neorv32.dtsi | 39 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 39 insertions(+)

diff --git a/dts/riscv/neorv32.dtsi b/dts/riscv/neorv32.dtsi
index 919eb7131a4..b5670bcfbf6 100644
--- a/dts/riscv/neorv32.dtsi
+++ b/dts/riscv/neorv32.dtsi
@@ -7,6 +7,7 @@
 /dts-v1/;
 
 #include <skeleton.dtsi>
+#include <dt-bindings/gpio/gpio.h>
 
 / {
 	cpus {
@@ -67,6 +68,44 @@
 			label = "UART_0";
 		};
 
+		gpio: gpio {
+			compatible = "simple-bus";
+			gpio-map-mask = <0xffffffe0 0xffffffc0>;
+			gpio-map-pass-thru = <0x1f 0x3f>;
+			gpio-map = <
+				0x00 0x0 &gpio_lo 0x0 0x0
+				0x20 0x0 &gpio_hi 0x0 0x0
+			>;
+			#gpio-cells = <2>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			gpio_lo: gpio@ffffffc0 {
+				compatible = "neorv32-gpio";
+				status = "disabled";
+				reg = <0xffffffc0 4 0xffffffc8 4>;
+				reg-names = "input", "output";
+				gpio-controller;
+				ngpios = <32>;
+				syscon = <&sysinfo>;
+				label = "GPIO_LO";
+				#gpio-cells = <2>;
+			};
+
+			gpio_hi: gpio@ffffffc4 {
+				compatible = "neorv32-gpio";
+				status = "disabled";
+				reg = <0xffffffc4 4 0xffffffcc 4>;
+				reg-names = "input", "output";
+				gpio-controller;
+				ngpios = <32>;
+				syscon = <&sysinfo>;
+				label = "GPIO_HI";
+				#gpio-cells = <2>;
+			};
+		};
+
 		uart1: serial@ffffffd0 {
 			compatible = "neorv32-uart";
 			status = "disabled";